Reset-Synchronized IQ Divider Circuit for Glitchless Clock Startup

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In high-speed transmission/reception systems, clock frequency divider circuits often experience glitches due to unsynchronized clock and enable signals, which can disrupt data recovery processes.

Innovation Solution

The proposed solution involves a clock frequency divider circuit comprising a reset retimer circuit, a clock buffer circuit, and an IQ divider circuit. This configuration generates a reset synchronization signal synchronized with the clock signal, which is then used to buffer and synchronize the clock signal, thereby preventing glitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a clock signal is provided to the divider circuit without synchronization with the enable signal, then the divider circuit can operate independently, but glitches occur in the output signal

Engineering Contradiction:

ImproveIndependent operation of divider circuitVSAvoidGlitch-free operation

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The reset signal is synchronized with the clock signal before being used to control the divider circuit operation. This preliminary synchronization ensures that the enable signal transitions occur at safe moments relative to the clock edges, preventing glitches while maintaining independent operation capability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A reset synchronization circuit is introduced as an intermediary between the independent divider circuit operation and the clock signal. This intermediary synchronizes the reset/enable signal with the clock signal, eliminating glitches without requiring the entire system to be clock-synchronized

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If the reset signal transitions immediately without buffering, then the response time is minimized, but timing mismatches with the clock signal cause glitches

Engineering Contradiction:

ImproveReset signal response speedVSAvoidSignal synchronization

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The reset signal is buffered in advance before being used to control circuit operation. This preliminary buffering allows the signal to be ready immediately while also providing an opportunity to synchronize its transitions with the clock signal, preventing glitches

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A buffer circuit is introduced as an intermediary between the reset signal source and the divider circuit control logic. This buffer provides both timing adjustment capability and signal strengthening, allowing fast response while maintaining synchronization with the clock signal

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12212645B2Reset synchronizing circuit and glitchless clock buffer circuit for preventing start-up failure, and IQ divider circuit

Publication Date: 2025.01.28 SAMSUNG ELECTRONICS CO LTD

AI summary

A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.