Reset Waveform Control Using On-Chip Instruction Memory
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Solution Overview
Problem
As circuitry becomes increasingly complex, the generation of reset signals to perform reset operations becomes complex and time-sensitive, requiring differentiation between multiple reset operations, especially in applications like digital micro-mirror devices (DMDs), where accurately timing reset signals is crucial for micro-mirror positioning, and existing off-chip waveform generation methods are limited by the speed of off-chip instruction transmission.
Innovation Solution
The implementation of on-chip and off-chip instruction-based reset controller circuitry that generates reset signals using bi-level and multi-level indicators, along with duration indicators, allowing for accurate and high-speed generation of reset signals by integrating on-chip and off-chip instructions, thereby simplifying integration complexity and enabling arbitrary waveform generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If off-chip waveform generation methods are used, then integration complexity is reduced, but generation speed is limited by off-chip instruction transmission speed
Solution Approach 1:
The waveform generation functionality is segmented into two parts: on-chip instruction processing for high-speed waveform generation and off-chip instruction processing for configuration and control. The on-chip instructions are stored in a memory array and executed by a controller, enabling fast waveform generation without being limited by off-chip transmission speed, while the off-chip interface provides a simplified configuration mechanism.
Solution Approach 2:
An intermediary memory array is introduced between the off-chip interface and the waveform generation circuitry. This memory array stores on-chip instructions that mediate between the slow off-chip instruction transmission and the fast on-chip waveform generation, allowing the system to achieve both high generation speed and simplified integration.
2Adaptability or versatility
If complex reset operations are performed, then functionality is improved, but reset operation duration increases
Solution Approach 1:
The reset controller circuitry dynamically adjusts the reset signal waveform based on real-time instructions from the memory array. The controller can modify waveform parameters such as pulse width, frequency, and amplitude on-the-fly, enabling complex reset operations to be performed efficiently without fixed time constraints, thus reducing overall reset duration while maintaining full functionality.
Solution Approach 2:
The system changes waveform parameters dynamically by receiving new instructions from the memory array that specify different pulse widths, frequencies, and amplitudes. This allows complex reset operations to be achieved through parameter modulation rather than extended time, maintaining functionality while reducing duration.
3Adaptability or versatility
If multiple reset operations are differentiated, then functionality is improved, but signal complexity increases
Solution Approach 1:
Different reset operations are differentiated by encoding specific control information locally in the on-chip instruction memory array. Each reset operation type has its own dedicated instruction set with specific parameters, allowing the system to generate diverse reset waveforms without requiring complex external signaling or additional differentiation circuitry, thus maintaining signal simplicity while achieving functional differentiation.
Data Source
AI summary
An example system includes an array of elements, each element of which including a controllable element and a data cell; a memory coupled to the array of elements to supply data to the array of elements; reset driver circuitry coupled to the array of elements to supply reset signals to the data cells; and reset controller circuitry coupled to the reset driver circuitry to generate the reset signals instructions including a bi-level reset indicator to control a first reset signal of the reset signals, a multi-level reset indicator to control a second reset signal of the reset signals, and a duration indicator to control timing of the reset signals.