Reset Waveform Generation Using Memory-Based Multi-Level Indicators
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Solution Overview
Problem
As circuitry becomes increasingly complex, the generation of reset signals becomes complex and time-sensitive, requiring methods to differentiate between multiple reset operations and synchronize with system clocks, while off-chip waveform generation is limited by the speed of external instruction transmission.
Innovation Solution
The implementation of on-chip and off-chip instruction-based reset controller circuitry that uses bi-level and multi-level reset indicators, along with duration indicators, to generate reset signals, allowing for arbitrary waveform generation at high speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex reset operations are performed to differentiate between multiple reset operations, then reset operation differentiation capability is improved, but reset signal generation complexity increases
Solution Approach 1:
The reset signal generation is segmented into multiple independent components: a multiplexer for selecting reset operation types, a state machine for generating waveform sequences, and a memory for storing waveform patterns. This segmentation allows each component to handle a specific aspect of reset operation differentiation without requiring the entire system to be overly complex.
Solution Approach 2:
The system uses a dynamic state machine that transitions between different states based on the selected reset operation type. The state machine generates different waveform sequences dynamically rather than requiring static complex circuitry for each possible reset operation, enabling versatile reset differentiation with manageable complexity.
2Speed
If reset signal generation speed is increased to meet time-sensitive requirements, then reset operation speed is improved, but waveform generation complexity increases
Solution Approach 1:
Waveform patterns are pre-stored in memory during normal operation. When a reset operation is needed, the system simply retrieves the pre-computed waveform sequence from memory rather than generating it in real-time through complex calculations. This preliminary action enables fast reset signal generation while keeping the generation logic relatively simple.
Solution Approach 2:
Instead of generating unique waveforms from scratch for each reset operation type, the system uses a state machine to copy and sequence pre-defined waveform patterns from memory. This copying approach enables rapid waveform generation at high speeds while maintaining manageable complexity in the generation circuitry.
3Adaptability or versatility
If multiple reset operations are supported to accommodate different circuitry requirements, then system adaptability is improved, but signal generation complexity increases
Solution Approach 1:
A single universal reset signal generation circuit performs multiple reset operations by selecting different waveform patterns from memory through a multiplexer and state machine. This multi-functional approach allows the same circuit to support various reset operations (e.g., normal reset, brown-out reset, wake-up reset) without requiring separate dedicated circuitry for each operation type.
Solution Approach 2:
The state machine acts as an intermediary between the reset operation selector and the waveform generation logic. It translates high-level reset operation requirements into specific waveform sequence selections from memory, mediating between the need for multiple operation support and the complexity of signal generation by introducing an intermediate control layer.
Data Source
AI summary
An example apparatus includes a multiplexer; a first memory coupled to the multiplexer; a second memory coupled to the multiplexer, the second memory including a bi-level reset indicator, a multi-level reset indicator, and a duration indicator; a memory controller coupled to the multiplexer; and waveform generation circuitry coupled to the memory controller, the waveform generation circuitry including: a first power supply configured to receive the bi-level reset indicator; a second power supply configured to receive the multi-level reset indicator; and timing circuitry configured to receive the duration indicator.