Residue-Based Packet Length Encoding for Scheduling Storage Reduction

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Solution Overview

Problem

Current packet scheduling systems face complexity and high storage requirements due to the need for precise packet lengths, which can lead to accumulated errors when using reduced bit resolution, making it challenging to manage large numbers of queues efficiently.

Innovation Solution

The method involves maintaining a residue amount for packet queues to adjust packet lengths, allowing for reduced bit storage while minimizing long-term errors by updating the residue based on packet lengths, enabling efficient scheduling with fewer bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If packet lengths are stored with full precision (14 bits), then scheduling accuracy is maintained, but storage requirements and device complexity increase

Engineering Contradiction:
Improvescheduling accuracyVSAvoidstorage requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The packet length is segmented into two parts: an encoded length value stored in SRAM control structures and a residue value stored in DRAM. The encoded length uses fewer bits for common values, while the residue compensates for the reduction. This segmentation allows the system to maintain scheduling accuracy while reducing the storage complexity in the critical SRAM path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter representation by introducing an encoding scheme that maps packet lengths to compressed values. Instead of storing the actual packet length directly, the system stores an encoded value that requires fewer bits, accompanied by a residue that captures the difference. This parameter transformation enables reduced storage requirements while preserving scheduling precision.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If packet length precision is reduced (fewer bits), then storage complexity decreases, but accumulated errors in scheduling increase

Engineering Contradiction:
Improvestorage requirementsVSAvoidscheduling accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The residue acts as an intermediary that bridges the gap between the compressed encoded length and the actual packet length. By storing and updating the residue in DRAM, the system recovers the precision information that would otherwise be lost in the compression process. This intermediary mechanism prevents accumulated errors while maintaining the benefits of reduced storage complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback by continuously updating the residue based on the difference between the encoded length and the actual packet length. This feedback loop ensures that any discrepancies are tracked and compensated for in subsequent scheduling operations, preventing error accumulation over time while maintaining reduced storage requirements.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If more queues are supported, then network capacity increases, but storage requirements for packet lengths increase linearly

Engineering Contradiction:
Improvenumber of queuesVSAvoidstorage requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the storage architecture into two tiers: SRAM for storing encoded length values and DRAM for storing residue values. This segmentation allows the system to support a large number of queues by distributing the storage burden across both memory types. The SRAM path remains compact and fast, while the DRAM provides the necessary capacity for handling many queues without linearly increasing the critical control structure size.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7349418B1Residue-based encoding of packet lengths of particular use in processing and scheduling packets
Publication Date: 2008.03.25 CISCO TECHNOLOGY INC
  • US7349418B1 patent drawing
  • US7349418B1 patent drawing
  • US7349418B1 patent drawing

AI summary

Processing a packet typically includes enqueuing the packet on to a queue when it arrives at a device, and then at some later time under control of the scheduler, dequeuing the packet for transmission. The scheduler needs some representation of the packet length for its uses when dequeuing. By storing the packet length as an adjusted packet length containing fewer bits, the scheduler and any storage of the packets lengths in the queues are reduced in complexity/size. One implementation maintains a residue amount corresponding to one or more packet queues or streams of packets. The residue amount is updated to maintain a forward looking or lagging behind indication of the error induced by this approximation. An adjusted packet length for the packet is determined based on its actual packet length and the residue amount. The residue amount is accordingly updated to reduce any long term error induced by using the adjusted packet lengths.