Resilient Data Move Instructions for PMEM

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Solution Overview

Problem

Host processors are not adequately configured to leverage the enhanced functionality of advanced persistent memory (PMEM) and storage class memory (SCM) devices due to limited instruction sets, resulting in suboptimal data resiliency and efficiency.

Innovation Solution

Incorporating resilient data move instructions into the host processor's instruction set, which allows for efficient data resiliency by moving data across multiple storage locations and ensuring data consistency across different storage domains, even in the presence of failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the host processor uses a limited instruction set, then the device complexity is reduced, but the ability to leverage enhanced functionality of advanced PMEM and SCM devices is insufficient

Engineering Contradiction:
Improveability to leverage enhanced functionality of advanced PMEM and SCM devicesVSAvoidinstruction set complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces specialized data move instructions that are pre-configured to handle resilient data movement operations. These instructions are designed in advance to automatically perform complex operations including identifying multiple storage locations, moving data with resiliency checks, and managing fault tolerance, thereby enabling the processor to leverage advanced PMEM and SCM functionality without requiring complex runtime logic

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the host processor implements resilient data move instructions, then data resiliency is enhanced, but the instruction set complexity increases

Engineering Contradiction:
Improvedata resiliencyVSAvoidinstruction set complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The resilient data move instructions are designed to autonomously perform resiliency operations without requiring external intervention. The instructions automatically identify multiple storage locations, execute data movement with built-in resiliency checks, and handle fault tolerance mechanisms independently, thereby enhancing data reliability while maintaining a relatively simple instruction set architecture

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent combines multiple operations into single resilient data move instructions. These merged instructions simultaneously perform data movement, resiliency verification, and fault tolerance management in one atomic operation, reducing the need for multiple separate instructions and minimizing instruction set complexity while maximizing data reliability

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If data is moved to multiple distinct storage locations, then data resiliency is improved, but the data movement efficiency may be reduced

Engineering Contradiction:
Improvedata resiliencyVSAvoiddata movement efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The processor identifies multiple distinct storage locations in advance before executing the data move operation. By pre-configuring the target locations and preparing the resiliency check mechanisms, the system can perform parallel or optimized sequential data movement, reducing the overall time penalty associated with writing to multiple locations while maintaining enhanced data resiliency

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10922078B2Host processor configured with instruction set comprising resilient data move instructions
Publication Date: 2021.02.16 EMC IP HLDG CO LLC
  • US10922078B2 patent drawing
  • US10922078B2 patent drawing
  • US10922078B2 patent drawing

AI summary

A system includes a host processor and at least one storage device coupled to the host processor. The host processor is configured to execute instructions of an instruction set, the instruction set comprising a first move instruction for moving data identified by at least one operand of the first move instruction into each of multiple distinct storage locations. The host processor, in executing the first move instruction, is configured to store the data in a first one of the storage locations identified by one or more additional operands of the first move instruction, and to store the data in a second one of the storage locations identified based at least in part on the first storage location. The instruction set in some embodiments further comprises a second move instruction for moving the data from the multiple distinct storage locations to another storage location.