Resilient IC Design for Hardware Trojan Counteraction
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Solution Overview
Problem
Current fault-tolerant integrated circuit (IC) designs are inadequate in counteracting malicious alterations, specifically hardware Trojans, which can disrupt IC functionality, and existing models are limited to random faults, not addressing deliberate and non-random faults effectively.
Innovation Solution
A method for designing resilient ICs that incorporates techniques from probabilistically checkable proofs and sorting networks to provide redundancy and robustness, allowing ICs to maintain functionality even with malicious alterations by transforming the combinatorial part of the IC into a family of circuits with specific completeness and soundness properties, and using ε-halvers to combine these circuits fault-tolerantly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault-tolerant IC designs based on random fault models are used, then they can handle random errors, but they fail to counteract deliberate hardware Trojans and malicious alterations
Solution Approach 1:
The IC circuit is divided into multiple segments or modules, each processed independently through the fault-tolerance construction. The combinatorial circuit is segmented into sub-circuits that can be individually analyzed and protected, allowing the system to tolerate malicious alterations in some segments while maintaining overall functionality.
Solution Approach 2:
The invention transforms the circuit design from a single-layer approach to a multi-dimensional construction by introducing hierarchical levels of protection. The fault-tolerance construction adds dimensional layers including input encoding, circuit decomposition into levels, and output decoding, creating a multi-dimensional structure that resists malicious alterations.
2Reliability
If the IC design incorporates fault-tolerance mechanisms for malicious alterations, then reliability against hardware Trojans improves, but the design complexity and construction difficulty increase
Solution Approach 1:
The fault-tolerance mechanisms are built into the IC design during the manufacturing process rather than added later. The combinatorial circuit is pre-processed to identify critical gates and wires, and protection mechanisms are incorporated into the fabrication process itself, making the resilient design as manufacturable as traditional designs.
Solution Approach 2:
The IC circuit performs self-diagnosis and self-protection through the fault-tolerance construction. The circuit monitors its own operation and automatically compensates for malicious alterations without requiring external intervention, maintaining functionality through internal redundancy and verification mechanisms.
3Reliability
If existing fault-tolerant models like von Neumann's random fault model are applied, then random errors are handled, but deliberate non-random faults from hardware Trojans remain unaddressed
Solution Approach 1:
The fault-tolerance construction applies different protection strategies to different parts of the circuit based on their vulnerability. Critical gates and wires that are more susceptible to hardware Trojans receive enhanced protection, while less critical components use standard protection, optimizing the balance between reliability and redundancy.
Solution Approach 2:
The invention changes the fundamental parameters of the fault model from random probability distributions to deliberate adversarial alteration patterns. The design parameters are adjusted to account for worst-case scenarios where an adversary intentionally modifies specific gates and wires, rather than assuming random failures.
Data Source
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AI summary
Computer-implemented method for constructing a fault-tolerant integrated circuit, IC, comprising a plurality of gates and a plurality of wires. The method comprises the steps of: providing a Boolean function to be realised as a fault-tolerant Boolean circuit within the IC; providing a looseness δ ; providing a gate fault-tolerance α according to the maximum fraction of faulty gates; providing a wire fault-tolerance β according to the maximum fraction of faulty wires; deciding whether the Boolean function is symmetric. If the Boolean function is symmetric, a fault-tolerant Boolean circuit realisation of it by using δ -loose realisations of threshold functions is constructed. Otherwise, the following steps are performed: implementing a family of Boolean circuits; implementing a combination of the outputs of the family of circuits by AND gates.