Self-Assembled Resilient Leads for Wafer-Level Packaging
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Solution Overview
Problem
Wafer-level packaging techniques are limited in their application to larger integrated circuit chips due to thermal expansion mismatches between the chip and the printed circuit board, causing stress and cracks during thermal cycling and drop tests, and the high stiffness of solder leads to additional stress issues.
Innovation Solution
The implementation of self-assembled resilient leads that can flex to absorb stress, configured to move from a retracted position adjacent to the chip to an extended position for interconnection, with a guard for protection and optional attachment bumps for mechanical and electrical attachment to the printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional rigid solder leads are used to interconnect larger integrated circuit chips to printed circuit boards, then electrical connection is achieved, but thermal expansion mismatch causes stress and cracks during thermal cycling
Solution Approach 1:
The patent changes the physical state and mechanical properties of the lead material by using a resilient alloy composition (e.g., tin-silver-copper-gold) that exhibits different thermal expansion characteristics and elastic properties compared to traditional rigid solder. This allows the lead to accommodate thermal expansion mismatch through elastic deformation, reducing stress and preventing cracks during thermal cycling while maintaining reliable electrical connection.
2Stability of the object's composition
If traditional rigid solder leads are used for interconnection, then structural stability is maintained, but the high stiffness causes additional stress during drop tests
Solution Approach 1:
The patent transitions from a static rigid structure to a dynamic resilient structure. The leads are designed with controlled flexibility allowing them to bend and absorb impact energy during drop tests, then return to their original position. This dynamic behavior reduces peak stress during impact events while maintaining structural integrity and electrical connection stability under normal operating conditions.
3Productivity
If wafer-level packaging is applied to larger integrated circuit chips, then manufacturing efficiency is improved, but thermal expansion mismatch causes stress and cracks
Solution Approach 1:
The patent modifies the material parameters of the lead alloy to create a composition with optimized elastic modulus and thermal expansion coefficient. This resilient material enables wafer-level packaging of larger chips by accommodating the greater thermal expansion mismatch that occurs with larger device areas, maintaining both manufacturing efficiency and device reliability simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the successful fabrication and assembly of wafer-level packaged devices with larger integrated circuit chips by mitigating stress and deformation issues, enhancing reliability and reducing the risk of damage during thermal cycling and drop tests.
Implementation Method 1
Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board
Data Source
AI summary
A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.