Resilient Memory Error Handling via Exception Suppression
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Solution Overview
Problem
Existing error handling mechanisms in computing systems raise unnecessary exceptions when errors occur in resilient memory regions, leading to significant overhead and performance degradation.
Innovation Solution
A method and apparatus for error handling in resilient software that identifies regions of resilient memory using thread-specific registers and translates virtual addresses to physical addresses to prevent exceptions from being raised when errors occur within these regions, allowing errors in resilient memory to be ignored and exceptions for non-resilient regions to be handled as usual.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exception handling is raised for all memory errors, then system reliability is improved, but system performance deteriorates due to unnecessary overhead
Solution Approach 1:
The patent applies local quality by differentiating between resilient and non-resilient memory regions. Errors in resilient memory regions are handled differently (suppressed) compared to errors in non-resilient regions (exception raised). This is implemented through separate error suppression registers that selectively control exception behavior based on the memory region being accessed, allowing the system to optimize for performance in resilient regions while maintaining reliability in non-resilient regions.
2Productivity
If exception suppression is enabled for resilient memory regions, then system performance is improved, but system reliability may worsen if errors are not properly managed
Solution Approach 1:
The patent segments memory into distinct resilient and non-resilient regions, each with different error handling policies. Error suppression registers are segmented to correspond to specific memory regions, allowing independent control of exception behavior for each region. This segmentation enables the system to suppress exceptions in resilient regions for performance while maintaining proper error handling in non-resilient regions for reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the error suppression registers provide information back to the exception handling logic. When an error is detected, the system queries the suppression register to determine whether the error occurred in a resilient or non-resilient region, and accordingly decides whether to suppress or propagate the exception. This feedback loop ensures that reliability is maintained through informed decision-making.
3Measurement precision
If virtual address translation is performed to identify resilient memory regions, then error handling precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring error suppression registers with the virtual address ranges of resilient memory regions before error handling is needed. When virtual address translation occurs, the translated physical address can be directly compared against pre-established resilient region boundaries, eliminating the need for complex real-time analysis of memory region properties during error handling.
Data Source
AI summary
Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.