Resist Pattern Ion Trimming for Reduced Line-End Spacing
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Solution Overview
Problem
Current EUV lithography processes face limitations in reducing 2D dimensions (line end to line end spacing) while maintaining 1D dimensions (line width) in semiconductor manufacturing, which is essential for advanced process nodes as miniaturization continues, requiring improved methods to achieve smaller feature sizes.
Innovation Solution
The method involves forming a patterned resist layer and treating it with ion implantation from opposing directions to reduce the line end to line end spacing without significantly enlarging the line width, using a combination of tilt and rotation angles in an ion implanter to trim the resist patterns, allowing for subsequent etching processes to form smaller metal lines and circuit features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is applied to reduce line end to line end spacing, then the spacing is reduced by 5 nm to 6 nm, but the line width is slightly increased
Solution Approach 1:
The patent applies ion implantation with specific parameters (ion type, energy, dose, tilt angle) to modify the resist pattern. By changing the physical and chemical state of the resist through controlled ion bombardment, the line end spacing is reduced while maintaining acceptable line width dimensions. The tilt angle parameter is specifically optimized to achieve directional trimming of line ends.
Solution Approach 2:
The ion implantation process is performed as a preliminary treatment before the final etching step. This preliminary action modifies the resist pattern dimensions in advance, allowing the subsequent etching process to produce the desired final dimensions with improved line end to line end spacing.
2Measurement precision
If EUV lithography is used for patterning, then the resolution is improved with pitch≤35 nm, but the line end to line end spacing cannot be sufficiently reduced
Solution Approach 1:
The patent introduces ion implantation as an intermediary process between lithography and etching. This intermediate treatment modifies the lithographically formed resist pattern to achieve the desired dimensional adjustments that lithography alone cannot provide, specifically reducing line end to line end spacing while preserving the benefits of EUV lithography resolution.
Solution Approach 2:
The ion implantation process changes the physical and chemical parameters of the resist material, altering its properties to enable dimensional modification. This parameter change allows the resist to be trimmed in a controlled manner, achieving reduced line end spacing that complements the lithography resolution.
3Productivity
If continuous scaling down of geometry size is pursued, then production efficiency is improved and costs are lowered, but the complexity of processing and manufacturing increases
Solution Approach 1:
The ion implantation process serves multiple functions: it acts as a trimming process for line end spacing, a pre-treatment for etching, and a method for achieving dimensional control. This multi-functionality allows a single process step to address multiple requirements, reducing overall processing complexity despite continued scaling.
Solution Approach 2:
By changing the parameters of existing processes (ion implantation energy, dose, tilt angle), the same equipment and basic process methodology can be adapted to different scaling requirements, reducing the need for entirely new process tools and methods as geometry sizes continue to decrease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the line end to line end spacing by 5 nm to 6 nm while slightly increasing the line width, enhancing the resolution and precision of semiconductor manufacturing by integrating the process with existing lithography and etching techniques.
Implementation Method 1
first implanting ions into the resist pattern with the structure and the resist pattern at the first position; second implanting ions into the resist pattern with the structure and the resist pattern at the second position
Data Source
AI summary
A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.


