Three-Layer Resist Mask for Uniform Josephson Junction Resistance
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Solution Overview
Problem
Existing two-step deposition processes for quantum information processing devices, such as Josephson junctions, result in non-uniform junction resistances due to shadowing effects and grain growth variations, leading to inconsistent performance across multiple devices.
Innovation Solution
A three-layer resist mask is employed, where each layer has aligned openings with specific widths and orientations to minimize shadowing effects and grain growth, ensuring uniform deposition and reducing variations in junction dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a two-step deposition process is used to form quantum information processing devices, then the manufacturing process can be completed in two steps, but shadowing effects and grain growth variations cause non-uniform junction resistances and inconsistent performance
Solution Approach 1:
The patent divides the single thick resist mask into multiple thinner resist layers (first resist layer, second resist layer, third resist layer). Each layer has aligned openings that collectively define the final pattern. This segmentation reduces shadowing effects during deposition because each thinner layer casts less shadow, and the aligned openings ensure uniform material deposition through all layers, resolving the contradiction between productivity and manufacturing precision.
2Ease of manufacture
If angled deposition is performed to form junctions, then the deposition process can be completed, but shadowing effects cause variations in junction dimensions and resistance
Solution Approach 1:
The patent creates different local qualities in the resist mask structure by using multiple layers with different thicknesses and opening dimensions. The first, second, and third resist layers have progressively smaller opening widths (first opening width > second opening width > third opening width), which compensates for shadowing effects at different depths during angled deposition. This local variation in opening dimensions ensures uniform junction formation despite the angled deposition approach.
3Productivity
If grain growth is allowed during deposition, then the deposition process proceeds naturally, but grain growth variations lead to non-uniform junction resistances
Solution Approach 1:
The patent performs preliminary patterning of multiple resist layers with precisely aligned openings before the deposition process. This preliminary structuring creates a controlled template that guides material deposition uniformly across all junction sites. By establishing this precise geometric framework in advance, the patent prevents grain growth variations from causing resistance inconsistencies, as the aligned openings ensure uniform nucleation and growth conditions for all junctions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The technique enhances the uniformity of junction resistances and overall performance of quantum information processing devices by minimizing shadowing and grain growth effects, resulting in more consistent operating characteristics and improved yield.
Implementation Method 1
a first layer of material is deposited through the first opening, the second opening, and the third opening at a first deposition angle with respect to the substrate, and a second layer of material is deposited through the first opening, the second opening, and the third opening at a second deposition angle with respect to the substrate
Implementation Method 2
a surface oxidation of the first layer of material is performed to provide an oxidized region of the first layer of material prior to depositing the second layer of material
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (308), forming a first resist layer (310) on the dielectric substrate, forming a second resist layer (312) on the first resist layer, and forming a third resist layer (314) on the second resist layer. The first resist layer includes a first opening (316) extending through a thickness (311) of the first resist layer, the second resist layer (312) includes a second opening (318) aligned over the first opening and extending through a thickness (313) of the second resist layer, and the third resist layer (314) includes a third opening (320) aligned over the second opening and extending through a thickness (315) of the third resist layer.