Resistance Change Memory Device Adaptive Write Buffer Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistance change memory devices face challenges in stabilizing cell state transitions due to differences in parasitic resistance and capacitance across a highly integrated cell array, leading to difficulties in writing data with sufficient margin and achieving high-speed data transmission.
Innovation Solution
A resistance change memory device with a write buffer system that includes a current bypass circuit and a reference circuit to adjust the resistance value of a mimic word line, allowing for adaptive control of current flow and voltage supply to stabilize cell state transitions, thereby mitigating the effects of parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If highly integrated cell array is used to increase memory capacity, then storage density is improved, but parasitic resistance and capacitance variations across the array worsen, making it difficult to write data with sufficient margin
Solution Approach 1:
The patent applies local quality by adjusting the resistance value of mimic word lines according to the position of selected cells within the cell array. Different regions of the array have different parasitic characteristics, so the mimic word line resistance is locally optimized for each region to compensate for position-dependent variations in parasitic resistance and capacitance, enabling reliable data writing across the entire high-density array.
2Speed
If voltage operation is used for high-speed data transition, then write speed is improved, but circuit load increases, requiring larger circuit load capacity
Solution Approach 1:
The patent employs feedback by using sense amplifiers to detect the state of memory cells and control circuits to adjust write operations based on detected cell states. This feedback mechanism enables voltage operation for high-speed transitions while dynamically managing circuit load, as the control circuits can modulate write voltage amplitude and duration based on real-time cell state detection, preventing excessive power consumption.
3Reliability
If current operation is used for state transition, then data transition can be performed, but it takes longer time compared to voltage operation
Solution Approach 1:
The patent applies dynamics by switching between voltage operation and current operation modes depending on the specific data transition required. The system dynamically selects the appropriate operation mode: voltage operation for high-speed transitions when applicable, and current operation for transitions requiring higher reliability. This dynamic mode selection optimizes the balance between transition speed and reliability, reducing overall data transition time while maintaining necessary state change capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively stabilizes cell state transitions, enabling efficient data writing and high-speed data transmission in resistance change memory devices, even in large-capacity, highly integrated cell arrays.
Implementation Method 1
One of the features of an ReRAM cell is in that a state change operation from a high resistance state to a low resistance state and the other state change operation from the low resistance state to the high resistance state are different from each other in these electrical conditions. Explaining in detail, for example, the former is characterized as a 'voltage operation' while the latter is characterized as a 'current operation'.
Data Source
AI summary
A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it; and a write control circuit configured to make a part of current supplied to the selected memory cell flow out in accordance with the selected memory cell's state change in a write mode.