Resistance Change Memory Cell Sub-4F2 Patterning via Spacer Masking
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Solution Overview
Problem
Conventional methods for manufacturing memory devices using resistance change layers struggle to scale down the unit cell size to below 4F^2, where F=45 nm, limiting further miniaturization and integration.
Innovation Solution
A method involving the sequential stacking of conductive material, diode, and data storage layers, with precise etching and spacer formation to create a miniaturized structure, allowing for the reduction of unit cell size by forming holes and spacers to expose the data storage layer, enabling the formation of word and bit lines within a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for memory devices with resistance change layers, then the manufacturing process is relatively simple, but the unit cell size cannot be reduced below 4F^2
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages including forming first holes through the first interlayer insulating layer, forming first spacers on the sidewalls, forming second holes through the second interlayer insulating layer, and forming second spacers. This segmentation allows precise control of the unit cell structure to achieve size reduction below 4F^2 while maintaining manufacturing feasibility through systematic process steps
Solution Approach 2:
The invention transitions from planar patterning to three-dimensional spacer formation on sidewalls. By forming spacers vertically on the sidewalls of holes etched through multiple interlayer insulating layers, the process achieves sub-4F^2 unit cell dimensions by utilizing vertical dimension control rather than relying solely on lateral patterning resolution
2Productivity
If the unit cell size is reduced to below 4F^2, then the integration scale and storage density are improved, but the manufacturing process becomes more complex
Solution Approach 1:
The methodology performs preliminary actions by forming spacers on sidewalls before final patterning steps. The first spacers are formed on sidewalls of first holes, then second holes are formed through the second interlayer insulating layer, followed by forming second spacers. This preliminary spacer formation establishes precise geometric constraints that enable subsequent processing steps to achieve the required sub-4F^2 unit cell dimensions for high integration scale
Solution Approach 2:
The structure employs nested positioning where second holes are formed through the second interlayer insulating layer at locations defined by the first spacers, and second spacers are subsequently formed on sidewalls of second holes. This nested arrangement of holes and spacers across multiple interlayer insulating layers enables precise unit cell definition with area below 4F^2, achieving high storage density through systematic nesting
Data Source
AI summary
A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.