Resistance Change Memory Cell Array Reference Integration
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Solution Overview
Problem
In resistance change memory technologies, using a reference cell as a reference electric current generation resistance increases chip size and power consumption due to the need for multiple reference cells and dual word line activation.
Innovation Solution
A configuration where a reference cell is used as a reference electric current generation resistance, reducing the number of reference columns and allowing single-word line activation for both normal and reference cells, thereby minimizing chip size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple reference cells are used as reference electric current generation resistances, then data accuracy is improved, but chip size increases
Solution Approach 1:
The patent merges the reference cell function into the existing memory cell array by using a memory cell in the array as the reference electric current generation resistance. This eliminates the need for separate reference cells in dedicated reference columns, thereby reducing chip area while maintaining data accuracy through the use of a shared reference mechanism.
Solution Approach 2:
The patent implements multi-functionality by enabling memory cells to serve dual purposes: normal memory operation and reference electric current generation. By allowing a memory cell in the array to function as a reference cell, the system reduces the total number of dedicated reference components while maintaining the required reference current for accurate reading.
2Measurement precision
If multiple reference cells are used, then data accuracy is improved, but power consumption increases
Solution Approach 1:
The patent combines the reference cell functionality with existing memory cell operations, eliminating the need for separate reference cell activation circuits. This integration reduces the total power consumption by avoiding dual word line activation while maintaining data accuracy through the shared reference mechanism.
Solution Approach 2:
The patent enables memory cells to perform multiple functions including normal storage and reference current generation, thereby reducing the overall power consumption by eliminating dedicated reference cell power supply paths and activation logic.
3Reliability
If dual word line activation is used to select normal and reference cells, then reading operation reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the selection of normal memory cells and reference cells into a single word line activation operation. By using the same word line for both cell types, the system maintains reading operation reliability while significantly reducing the control complexity associated with managing multiple word lines.
Solution Approach 2:
The patent implements a universal word line that serves multiple functions: selecting both normal memory cells and reference cells. This multi-functional word line approach maintains the reliability of reading operations while simplifying the overall device control architecture by eliminating the need for separate word line control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area size of the memory cell array and decreases the electric power required for word line activation during read operations, while maintaining data accuracy by using a single word line for selecting both normal and reference cells.
Implementation Method 1
data '1' or '0' is determined by using a change in the resistance value when an electric current (or a voltage) is applied
Data Source
AI summary
A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.