Resistance-Change Memory Cell Layout Using Segmented Bit Lines
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Solution Overview
Problem
The challenge in resistance-change memory technologies, such as MRAM, lies in the difficulty of forming contacts between bit lines and transistors without short circuits, which limits the use of low-resistance wiring materials like copper, resulting in reduced read margins due to the necessity of using high-resistance materials like tungsten.
Innovation Solution
The proposed solution involves a memory cell array layout where MTJ elements are arranged to sandwich word lines, allowing for single-layered bit lines and reducing the risk of short circuits, enabling the use of low-resistance materials while maintaining a compact memory cell size of 6F2, and implementing voltage control to prevent errors during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two layers of bit lines are used to reduce memory cell area, then the bit line pitch is decreased and memory cell area is reduced, but the contact formation becomes very difficult and short circuit risk increases
Solution Approach 1:
The patent divides the bit line function into two separate single-layer bit lines (first bit line and second bit line) that are spatially separated and connected through shared word lines, avoiding the need for complex multi-layer contact formation while achieving the same memory cell area reduction
Solution Approach 2:
The patent transitions from a vertical multi-layer bit line structure to a horizontal single-layer configuration where bit lines are arranged in different spatial positions and connected through word lines, solving the contact formation problem by changing the structural dimension
2Ease of manufacture
If high-resistance wiring material like tungsten is used to avoid short circuits, then contact formation becomes easier, but the read margin of the resistance-change memory is reduced
Solution Approach 1:
The patent separates the bit line paths into distinct first and second bit lines that connect to different terminals of the variable resistance element, eliminating the need for high-resistance materials by avoiding short circuit risks through spatial separation rather than material substitution
Solution Approach 2:
The patent introduces word lines as intermediary elements that connect the first and second bit lines to the variable resistance element, enabling low-resistance material usage while maintaining electrical isolation and preventing short circuits through the intermediary connection structure
Data Source
AI summary
According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements arranged in order in the first direction, the first variable resistance element and the second variable resistance element sandwich one word line therebetween, the third variable resistance element and the fourth variable resistance element sandwich one word line therebetween, a first pair includes the first and second variable resistance elements and a second pair includes the third and fourth variable resistance elements sandwich two word lines therebetween, and a column is constructed by repeating the layout in the first direction.