Resistance Change Memory Two-Step Write Mode
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Solution Overview
Problem
Resistance change memory devices face challenges in achieving high-speed write modes due to asymmetric characteristics between reset and set operations, particularly in terms of time requirements, which hinder the development of high-performance ReRAM with large capacity.
Innovation Solution
A resistance change memory device with a cell array that employs distinct write procedures for different data states, utilizing a '1' only write mode in voltage mode and a '0' write mode in current mode, along with ECC refresh mechanisms to ensure data reliability and separate read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset operation is performed in current mode, then the data can be written reliably, but the write time becomes several times to one hundred times longer than the set operation
Solution Approach 1:
The write operation is segmented into two distinct modes: voltage mode for set operations and current mode for reset operations. This segmentation allows each operation type to use the most appropriate write mode, optimizing both speed and reliability for each specific operation rather than using a single mode for all writes.
Solution Approach 2:
The patent implements dynamic write mode selection based on the data state being written. The system automatically switches between voltage mode and current mode depending on whether a set or reset operation is required, making the write operation adaptive rather than static. This dynamic approach resolves the contradiction by applying the right mode at the right time.
2Speed
If the set operation is performed in voltage mode, then the write speed is fast, but the reset operation requires significantly more time
Solution Approach 1:
The write operation is segmented into two distinct modes: voltage mode for set operations and current mode for reset operations. This segmentation allows each operation type to use the most appropriate write mode, optimizing both speed and reliability for each specific operation rather than using a single mode for all writes.
Solution Approach 2:
The patent changes the operational parameter (write mode) based on the operation type. Voltage mode is used for set operations where speed is critical, while current mode is used for reset operations where reliability is paramount. This parameter change strategy allows the system to optimize performance for each specific operation.
3Device complexity
If asymmetric characteristics between reset and set operations are not considered, then the device structure remains simple, but it becomes difficult to achieve high performance ReRAM with large capacity
Solution Approach 1:
The patent implements dynamic write mode selection based on the data state being written. The system automatically switches between voltage mode and current mode depending on whether a set or reset operation is required, making the write operation adaptive rather than static. This dynamic approach resolves the contradiction by applying the right mode at the right time.
Solution Approach 2:
The patent changes the operational parameter (write mode) based on the operation type. Voltage mode is used for set operations where speed is critical, while current mode is used for reset operations where reliability is paramount. This parameter change strategy allows the system to optimize performance for each specific operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient high-speed data writing and reading in ReRAM, enhancing the device's performance and capacity by isolating read and write operations and optimizing write procedures based on data states.
Implementation Method 1
the set operation is a voltage mode
Implementation Method 2
the reset operation is a current mode
Data Source
AI summary
A resistance change memory device including a cell array, in which memory cells are arranged, the memory cell being reversibly set in one of a first data state and a second data state defined in accordance with the difference of the resistance value, wherein the memory device has a data write mode including: a first write procedure for writing the first data in the cell array; and a second write procedure for writing the second data in the cell array.