Resistance Change Memory Write Control Circuit
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Solution Overview
Problem
Existing semiconductor memory devices using resistance change memory elements lack an appropriate writing method, leading to inefficiencies in setting and maintaining high and low resistance states.
Innovation Solution
A semiconductor memory device with a write control circuit that differentiates voltage pulses for memory cells based on their current resistance states, applying steep voltage falls for high resistance states and gradual falls for low resistance states to control the crystalline or amorphous states of the memory element's material, simplifying the writing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a resistance change memory element is used for nonvolatile storage, then data retention capability is improved, but the writing method becomes complex and inefficient
Solution Approach 1:
The patent applies parameter changes by modifying the voltage pulse characteristics (fall time, amplitude, width) to control the resistance state of memory cells. Different voltage parameters are used to set high resistance state (HRS), low resistance state (LRS), and intermediate resistance state (IRS), enabling efficient writing operations without complex control logic.
Solution Approach 2:
The patent segments the memory cell population into different groups based on their resistance states (HRS, LRS, IRS) and applies differentiated voltage pulse strategies to each group. This segmentation allows simultaneous optimization of writing speed and accuracy for different memory states without increasing overall system complexity.
2Speed
If voltage pulses are applied to set resistance states, then data writing speed is improved, but control precision for different resistance states deteriorates
Solution Approach 1:
The patent uses multiple voltage pulse parameters (amplitude, width, fall time) to precisely control resistance state transitions. By adjusting these parameters, the system achieves both fast writing speed and high control precision for setting different resistance states (HRS, LRS, IRS) in memory cells.
Solution Approach 2:
The patent employs periodic voltage pulse applications with specific timing characteristics to reliably set resistance states. The use of structured pulse sequences with controlled rise and fall times ensures precise control over memory cell states while maintaining high writing speeds through optimized pulse timing.
3Productivity
If steep voltage fall is used for high resistance state, then writing efficiency is improved, but differentiation from low resistance state writing becomes difficult
Solution Approach 1:
The patent differentiates writing modes by using distinct voltage pulse parameters: steep fall time for HRS, gradual fall time for LRS, and specific pulse widths for IRS. These parameter variations enable the control circuit to easily distinguish and execute different writing operations without increasing operational complexity.
Solution Approach 2:
The patent implements dynamic control of voltage pulse characteristics based on the desired resistance state. The control circuit dynamically adjusts pulse parameters (fall time, amplitude, width) according to the target state (HRS, LRS, or IRS), enabling efficient and easily differentiated writing operations through adaptive parameter modulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and simplified writing operations by eliminating the need to differentiate rising characteristics for high and low resistance states, ensuring accurate data storage in resistance change memory elements.
Implementation Method 1
a phase-change memory element
Implementation Method 2
The resistance change memory element is switchable between a high resistance state and a low resistance state
Implementation Method 3
controlling a crystalline or amorphous state of a main body of the memory element
Implementation Method 4
controlling a crystalline or amorphous state
Data Source
AI summary
A semiconductor memory device comprises a memory cell including a resistance change memory element and a write control circuit for setting a resistance state of the resistance change memory element. The write control circuit applies a first voltage signal when setting the resistance change memory element. The first voltage signal rises in a first rise time from a first reference voltage to a first predetermined voltage, maintains at the first predetermined voltage for a first predetermined time period, and then falls from the first predetermined voltage to the first reference voltage in a first falling time. The write circuit applies a second or third voltage signal according to the state being set in the resistance change memory element. In some examples, a predetermined voltage level of the third signal is applied for a period of time longer than a predetermined level of the first and second voltage signals.