Resistance Compensation Circuit for Nonvolatile Memory Arrays
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Solution Overview
Problem
Semiconductor memory apparatuses face increased power consumption due to the large resistance difference between memory cells located far and near to the word line and bit line decoders, which leads to higher drivability requirements for write and read circuits, resulting in inefficiencies.
Innovation Solution
A resistance compensation circuit is introduced to generate compensation resistance values based on the position of memory cells, dividing the memory cell array into regions and providing these values to the word lines and bit lines, ensuring all memory cells have similar wiring resistances, thereby reducing the resistance difference and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drivability of the write circuit and read circuit is increased to prevent write and read errors due to large resistance difference, then the reliability is improved, but the power consumption is increased
Solution Approach 1:
The patent applies local quality by providing different compensation resistance values to different memory cell regions based on their positions. Memory cells are divided into multiple regions, and each region receives a tailored compensation resistance value that matches its specific wiring resistance characteristics, thereby optimizing reliability locally without uniformly increasing power consumption across the entire memory apparatus.
Solution Approach 2:
The patent changes the resistance parameter dynamically by introducing a resistance compensation circuit that adjusts the compensation resistance value according to the position of the memory cell. This allows the system to adapt the resistance parameter to match the actual wiring resistance at each location, preventing read/write errors without requiring consistently high drivability that would increase power consumption.
2Reliability
If the drivability of the write circuit and read circuit is increased, then the reliability is improved, but the device complexity is increased
Solution Approach 1:
The patent introduces a resistance compensation circuit as an intermediary component that sits between the control logic and the memory cell array. This mediator generates appropriate compensation resistance values based on memory cell positions and provides them to the relevant circuits, thereby reducing the drivability requirements of the write and read circuits without significantly increasing overall device complexity.
Solution Approach 2:
The patent segments the memory cell array into multiple regions and assigns different compensation resistance values to each region. This segmentation allows the system to address reliability issues in a localized manner rather than requiring uniformly high drivability across the entire array, thereby reducing overall circuit complexity while maintaining reliability.
3Length of stationary object
If memory cells are located far away from the word line decoder and bit line decoder, then the wiring resistance is increased, but the access speed is decreased
Solution Approach 1:
The patent changes the resistance parameter by introducing compensation resistance values that are specifically tailored to the position of each memory cell. For memory cells located far from the decoders with higher wiring resistance, the compensation circuit provides higher compensation resistance values, thereby equalizing the total resistance across different regions and maintaining consistent access speeds regardless of wiring length.
Data Source
AI summary
A nonvolatile memory apparatus may include a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. The nonvolatile memory apparatus may include and a resistance compensation circuit configured to generate a compensation resistance value according to a position of a memory cell to be accessed.