Real-Time Resistance Estimation for Partially Routed IC Nets
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Solution Overview
Problem
Conventional methods for checking maximum resistance constraints in electronic circuit design are inefficient, requiring full routing of the net and multiple iterations to adjust wire segments manually or automatically, which is time-consuming and complex.
Innovation Solution
The development of EDA tools that dynamically estimate and render resistance in a partially routed net, allowing real-time adjustments to wire segments while editing, ensuring the resistance constraint is met without fully routing the net.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to check maximum resistance constraints, then the resistance constraint can be verified, but the process requires full routing of the net and multiple iterations which is time-consuming
Solution Approach 1:
The system performs preliminary resistance estimation during the routing process itself, rather than waiting for complete routing. The EDA tool dynamically estimates resistance of partially routed nets and provides real-time feedback, allowing designers to make adjustments before the routing is complete, thereby eliminating the need for multiple post-routing iteration cycles
Solution Approach 2:
The system implements continuous feedback by dynamically rendering and updating the estimated resistance value as the routing progresses. The EDA tool monitors the partially routed net and automatically updates the resistance estimate, providing real-time feedback to the designer without requiring manual re-calculation or complete routing
2Manufacturing precision
If manual routing and checking is performed, then the resistance can be adjusted, but the process requires many iterations and routing modifications
Solution Approach 1:
The EDA tool performs automatic resistance estimation and provides self-service by continuously monitoring the partially routed net and calculating the resistance estimate without requiring manual intervention. The system automatically updates the resistance value as routing progresses, eliminating the need for designers to manually calculate and re-calculate resistance through multiple iterations
Solution Approach 2:
The resistance estimation is made dynamic rather than static. The EDA tool continuously updates the resistance estimate as the routing progresses from partial to complete, allowing the resistance value to change dynamically with each routing modification rather than requiring complete re-calculation after each change
3Measurement precision
If the entire net is fully routed before checking, then the resistance constraint can be accurately verified, but the user cannot detect resistance issues during editing
Solution Approach 1:
The system performs preliminary resistance estimation on partially routed nets before the routing is complete. The EDA tool calculates the resistance estimate during the editing process, allowing users to detect and correct resistance issues early in the design process rather than waiting until after complete routing
Solution Approach 2:
The system provides real-time feedback by dynamically rendering the resistance estimate as the user edits the routing. The EDA tool continuously monitors the partially routed net and updates the resistance estimate, giving immediate feedback to the user during the editing process rather than waiting for complete routing
Data Source
AI summary
Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves design productivity. Unlike conventional systems, an EDA tool disclosed herein does not have to route the full net between two circuit devices to run design rule checking (DRC). Thus, the EDA tool does not require multiple iterations of fully routing a net and checking for DRC violations such that the maximum resistance constraint is not violated.