Resistance Memory Element Bit Line Segmentation for Reading Interference
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Solution Overview
Problem
Existing non-volatile memory devices, such as resistance RAM and phase change RAM, face issues with erroneous information reading due to interference from the resistance state of adjacent memory elements, leading to incorrect interpretation of data.
Innovation Solution
The proposed solution involves a memory element structure with a substrate, a conductive bit line, a resistance or phase change layer that switches with electrical signals, and a word line, where each memory element shares source, drain, and bit lines with adjacent elements but isolates them for reading, allowing precise voltage application and current measurement to distinguish between set and reset states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a cross bar array structure is used to integrate resistance memory elements, then device integration is improved, but reading interference from adjacent elements occurs
Solution Approach 1:
The patent segments the bit line into two separate lines: a first bit line for writing operations and a second bit line for reading operations. This segmentation prevents reading interference from adjacent memory elements while maintaining the integrated cross bar array structure, as the read operation on the second bit line does not activate adjacent resistance switching layers that would cause interference.
Solution Approach 2:
The patent introduces a channel region as an intermediary element between the source and drain regions. This channel region, controlled by a gate voltage, acts as a mediator that enables current flow only when the selected memory element is being accessed, thereby preventing current leakage through adjacent elements and eliminating reading interference.
2Ease of operation
If voltage is applied to read information from a selected resistance memory element, then data retrieval is enabled, but current flows through adjacent elements causing erroneous reading
Solution Approach 1:
The patent divides the bit line function into two separate physical lines: the first bit line dedicated to writing and the second bit line dedicated to reading. When reading, voltage is applied to the second bit line without activating the resistance switching layer, thus retrieving data without causing the high current that would flow through adjacent elements and cause erroneous readings.
Solution Approach 2:
The patent dynamically controls the channel region by applying gate voltage only when needed. During reading operations, the channel region is configured to prevent current flow through unselected elements, while during writing operations, the channel region allows current flow. This dynamic control ensures precise reading without interference from adjacent elements.
3Device complexity
If the same bit line is used for both writing and reading, then device complexity is reduced, but writing and reading processes interfere with each other
Solution Approach 1:
The patent segments the bit line into two separate lines (first bit line for writing, second bit line for reading) to eliminate the interference between writing and reading operations. This segmentation allows each operation to be performed independently without affecting the other, improving operation reliability while maintaining relatively simple device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ON/OFF current ratio and prevents erroneous reading by separating the writing and reading processes, ensuring accurate data retrieval without interference from adjacent elements.
Implementation Method 1
a resistance switching layer formed between a bit line and a word line perpendicular to each other; the resistance switching layer switches resistance between high and low in response to an applied electrical signal
Implementation Method 2
a phase change layer formed between a bit line and a word line perpendicular to each other; when the phase change layer is crystalline, it corresponds to a low resistance state; when the phase change layer is amorphous, it corresponds to a high resistance state
Data Source
AI summary
A resistance memory element, a phase change memory element, a resistance random access memory device, an information reading method thereof, a phase change random access memory device, and an information reading method thereof are provided. The resistance random access memory device includes an array of resistance memory element arranged in a matrix. Each resistance memory element includes a substrate in which a source region and a drain region are formed along the column direction and a channel region is formed between the source region and the drain region, a bit line formed on the channel region out of a conductive material to have a shape extending along the arrangement direction of the columns, a resistance switching layer formed on the bit line out of a material of which electrical resistance is switched by an electrical signal, and a word line formed on the resistance switching layer out of a conductive material to have a shape extending along the row direction.