Resistance Memory Cell With Bridge Current Path
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Solution Overview
Problem
Conventional resistance memory cells face device degradation and reliability issues due to high current stress during erasing operations, especially in unipolar switching modes, and struggle to achieve high-density memory arrays due to transistor layout requirements in bipolar switching modes.
Innovation Solution
A resistance memory cell design that includes a second current path not passing through the metal oxide layer, using a tungsten metal layer and a second electrode with a bridge portion, allows for adjusting the resistivity of the metal oxide layer through either a first current path passing through it or a second current path extending between connection pads, preventing device degradation and enabling high-density memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If unipolar switching mode is used with increased voltage pulse amplitude and duration for erasing, then erasing capability is improved, but current stress increases causing device degradation and reduced reliability
Solution Approach 1:
The patent divides the current path into two separate paths: a first current path through the metal oxide layer for programming, and a second current path through the tungsten layer for erasing. This segmentation allows independent optimization of each operation, enabling strong erasing capability through the second path without subjecting the metal oxide layer to excessive current stress, thus preventing device degradation while maintaining reliability.
2Ease of operation
If bipolar switching mode is used with transistor switches for controlling each memory cell, then switching control is improved, but layout area increases reducing memory density
Solution Approach 1:
The patent merges the switching function into the shared word line structure rather than requiring individual transistor switches for each memory cell. The tungsten layer and bridge portion enable cross-point architecture where word lines and bit lines intersect to form memory cells, eliminating the need for dedicated transistor switches and significantly reducing layout area for high-density memory arrays.
3Reliability
If second current path is introduced not passing through metal oxide layer, then device degradation is prevented and reliability is improved, but structure complexity increases
Solution Approach 1:
The tungsten layer serves multiple functions: it acts as the second electrode, provides the low-resistance second current path for erasing, and functions as a heating element during erasing operations. The bridge portion similarly serves as both a structural connector and an electrical pathway. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in structural complexity while achieving improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents device degradation, improves memory reliability, and allows for high-density memory arrays by using the second current path to set the metal oxide layer to a low resistance state without passing through it, reducing current stress and eliminating the need for transistor switches.
Implementation Method 1
the resistance memory cell generates a heat source through the second current path and reduces the resistivity of the metal oxide layer by the heat source
Data Source
AI summary
A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.