Resistance Variable Memory Cell Programming and Erasing Control
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Solution Overview
Problem
Conventional semiconductor memory devices with resistance variable memory cells face challenges in programming and erasing operations due to limited drive current and power dissipation, particularly in maintaining a substantially constant common source potential to reduce write delay and power consumption.
Innovation Solution
The implementation of a resistance variable memory cell architecture that programs or erases cells in two acts by adjusting the control gate voltage and data line potential, allowing for higher drive current through a field-effect transistor access device, with specific voltage pulses for programming and erasing to manage the gate-source voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional programming and erasing operations are used with limited drive current, then power dissipation is reduced, but programming and erasing speed deteriorates
Solution Approach 1:
The programming and erasing operations are divided into two distinct acts: a first act that switches the access device to conductive state, and a second act that applies the programming or erasing voltage. This segmentation allows the drive current to be elevated only during the brief switching phase rather than maintained throughout the entire operation, thereby improving speed while limiting overall power dissipation.
Solution Approach 2:
The patent employs periodic voltage pulses with specific timing characteristics to control the access device. A first voltage pulse switches the access device on, followed by a second voltage pulse that performs the actual programming or erasing. This periodic action pattern enables high drive current to be applied intermittently rather than continuously, resolving the contradiction between speed and power consumption.
2Loss of time
If common source potential is maintained substantially constant to reduce write delay, then programming speed is improved, but power dissipation increases
Solution Approach 1:
The operation is segmented into phases where the common source potential is held constant only during the critical switching phase to minimize write delay, while allowing potential variation during the actual programming/erasing phase. This selective maintenance of constant potential reduces both write delay and overall power dissipation compared to maintaining constant potential throughout the entire operation.
Solution Approach 2:
The common source potential is dynamically adjusted during the programming and erasing operations rather than being held strictly constant. The potential is maintained at a first level during the first act to reduce write delay, then adjusted to a second level during the second act to manage power dissipation, optimizing both performance and energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the drive current in resistance variable memory cells, improving performance by maintaining efficient programming and erasing operations while minimizing power dissipation and write delay.
Implementation Method 1
a field-effect transistor access device, with specific voltage pulses for programming and erasing to manage the gate-source voltage effectively
Data Source
AI summary
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.