Resistance Variable Memory Cell State Synchronization
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Solution Overview
Problem
Resistance variable memory cells experience resistance drift over time, leading to erroneous reading and increased energy consumption in existing approaches that attempt to correct for drift by tracking time or always rewriting all cells, which is costly and power-intensive.
Innovation Solution
Implementing data state synchronization by resetting all memory cells in a group to a uniform state before a write operation, eliminating the need to track drift time and reducing energy consumption by only applying reset signals to cells not already in the reset state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If drift time is tracked and cells are refreshed based on time, then resistance drift is corrected, but device complexity and energy consumption increase
Solution Approach 1:
The patent extracts the time-tracking mechanism from the memory system and replaces it with a time-independent synchronization approach. Instead of monitoring drift time and making decisions based on time thresholds, the system uses status flags and uniform reset operations that do not require time measurement or tracking infrastructure.
Solution Approach 2:
The patent creates a universal managed unit status that applies to all memory cells regardless of individual programming times. The synchronization status flag provides a unified state that indicates whether uniform reset is needed, eliminating the need for cell-specific time tracking and enabling batch processing of entire memory blocks.
2Reliability
If all memory cells are always rewritten to correct drift, then data accuracy is maintained, but energy consumption increases
Solution Approach 1:
The patent applies partial action by performing uniform reset only on cells that need it, as indicated by the synchronization status flag. Instead of rewriting all cells regardless of their state, the system selectively applies reset signals only to managed units where the status indicates non-uniform states exist, reducing unnecessary programming operations and associated energy consumption.
Solution Approach 2:
The memory system performs self-diagnosis through status flags that indicate whether uniform reset is needed, and automatically executes the synchronization operation without external intervention. The system monitors its own state and triggers corrective actions only when necessary, eliminating the need for continuous external monitoring and control.
3Reliability
If continuous monitoring and refreshing is performed, then resistance drift is compensated, but power consumption increases
Solution Approach 1:
The patent implements periodic action through background operations that periodically check and synchronize managed unit statuses. Instead of continuous monitoring, the system performs status checks and uniform reset operations at intervals, reducing power consumption while maintaining data reliability. The lazy evaluation approach delays synchronization until necessary, performing it periodically rather than continuously.
Solution Approach 2:
The patent uses inexpensive status flags as temporary indicators of synchronization needs. These flags are simple binary states that require minimal power to maintain, replacing complex continuous monitoring systems. The flags are updated only when needed and do not require persistent power to retain their state, functioning as disposable indicators that are reset along with the memory cells.
4Adaptability or versatility
If non-uniform cell states are allowed, then programming flexibility is maintained, but read errors increase due to drift
Solution Approach 1:
The patent applies preliminary action by performing uniform reset operations before write operations on managed units. By synchronizing all cells to a known uniform state beforehand, the system ensures that subsequent programming operations start from a consistent baseline, preventing the accumulation of non-uniform states that could lead to read errors while maintaining full programming flexibility during normal operations.
Data Source
AI summary
The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.