Resistance Variable Memory Reference Cell Sensing
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Solution Overview
Problem
Resistance variable memory devices, such as PCRAM and RRAM, face reliability issues due to temperature changes affecting the resistance characteristics of phase change materials like GST, leading to errors in sensing operations.
Innovation Solution
Incorporating reference cells embedded with data cells to create a sensing scheme that is less susceptible to temperature changes, allowing for accurate determination of data states by comparing sensed levels between data and reference cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistance variable memory devices use phase change materials like GST, then memory storage capability is achieved, but temperature changes affect resistance characteristics leading to sensing errors
Solution Approach 1:
The patent introduces reference cells as intermediary elements that mediate between the data cells and the sensing operation. These reference cells experience the same temperature changes but do not store data, serving as a reference baseline to compensate for temperature-induced resistance variations in the data cells.
Solution Approach 2:
The sensing operation uses feedback by comparing the resistance of data cells with reference cells. The reference cells provide feedback information about temperature effects, allowing the system to distinguish between resistance changes due to stored data versus those due to temperature variations.
2Reliability
If reference cells are embedded with data cells, then temperature immunity is enhanced, but device complexity increases
Solution Approach 1:
The patent merges reference cells with data cells in the same memory array structure, using identical cell configurations and interconnects. This integration allows both cell types to share the same physical infrastructure, reducing overall device complexity while maintaining temperature compensation functionality.
Solution Approach 2:
The reference cells use the same phase change material and structural design as data cells, making the cell design universal. This multi-functionality allows the same cell structure to serve either as data storage or temperature reference, simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the immunity of resistance variable memory devices to temperature changes, ensuring accurate data state determination and improving the reliability of both single-level and multilevel memory systems.
Implementation Method 1
The memory cell material of a PCRAM device, e.g., GST, can exist in an amorphous, high resistance state, or a crystalline, low resistance state. The resistance state of the PCRAM cell, e.g., the GST, can be altered by applying current pulses to the cell. For example, the resistance state of the PCRAM cell, e.g., the GST, can be altered by heating the cell with a programming current.
Implementation Method 2
The resistance of a resistance variable memory cell can be sensed in order to determine the data state of the cell. During a sensing operation, the resistance of a selected memory cell can be compared to a reference resistance in order to determine if the memory cell has a greater or lesser resistance, thereby indicating the content of the stored data.
Data Source
AI summary
The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.