Variable Resistance Memory Cell Resetting Voltage Control
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Solution Overview
Problem
In resistance change memory devices, the repeated setting and resetting operations lead to variable resistance element deterioration, causing increased leak current and difficulty in completing the resetting mode, which can result in reduced memory cell lifespan if excessive voltages are applied due to unadjusted resetting verify voltages.
Innovation Solution
A control circuit dynamically adjusts the resetting verify voltage based on the degree of deterioration of the memory cells by employing a judgment mode that counts the number of cells attaining a conductive state after a resetting operation, allowing for appropriate voltage adjustments to ensure successful resetting without accelerating deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed resetting verify voltage is applied to all memory cells, then the initial resetting operation can be completed, but the operation time becomes non-uniform and excessive voltage may be applied to deteriorated cells as they age
Solution Approach 1:
The patent implements dynamic adjustment of the resetting verify voltage based on the operational state and deterioration level of memory cells. Instead of using a fixed voltage threshold, the system adapts the voltage level according to feedback from judgment mode operations, allowing the resetting process to accommodate aging effects and maintain both speed and reliability throughout the device lifecycle
Solution Approach 2:
The patent employs a feedback mechanism where the judgment mode counts the number of memory cells attaining conductive state during resetting operations. This count information is used to adjust subsequent resetting verify voltages, creating a closed-loop control system that prevents excessive voltage application and optimizes operation timing based on actual cell behavior
2Reliability
If the resetting verify voltage is increased to ensure complete resetting of all cells, then resetting reliability improves, but the operation time increases and cell deterioration accelerates
Solution Approach 1:
The patent applies partial action by adjusting the resetting verify voltage to match the actual needs of the memory cell population. Rather than always applying the maximum voltage needed for the most deteriorated cell, the system uses just enough voltage to achieve complete resetting for the current operational state, thereby reducing unnecessary time loss and stress on cells
Solution Approach 2:
The patent dynamically changes the voltage parameter based on the operational history and deterioration level of memory cells. By monitoring the count of cells attaining conductive state and adjusting the verify voltage accordingly, the system optimizes the balance between resetting reliability and operation time, preventing both incomplete resetting and excessive time consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform operation time for resetting and extends the lifespan of memory cells by preventing excessive voltage application, maintaining the integrity of the memory device.
Implementation Method 1
The variable resistance film has a resistance value that changes by applying a required voltage or current to the variable resistance film
Data Source
AI summary
This semiconductor memory device comprises: a memory cell array configured as an arrangement of memory cells disposed at intersections of a plurality of first lines disposed substantially in parallel and a plurality of second lines disposed to intersect the first lines, each of the memory cells including a variable resistance element; and a control circuit configured to control the memory cell array. The control circuit is configured to change a voltage value of a resetting verify voltage applied for confirming completion of the resetting operation according to a degree of change of resistance of the memory cell when performing the resetting operation to change the memory cell from a low-resistance state to a high-resistance state.