Resistance Memory Device Segmented Word Line Control
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Solution Overview
Problem
Current resistance memory devices face challenges in achieving ultra-high integration and low power consumption while efficiently fabricating and operating, as existing methods are complex and require high integration with 3D structures and horizontal channel transistors.
Innovation Solution
The proposed resistance memory device employs a data storage unit connected to access devices via interconnections, with a controller and read/write control circuit to manage operations, using a semiconductor substrate with specific layer formations and voltage control to drive access devices, allowing for efficient switching between resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional resistance memory devices use complex fabrication methods with 3D structures and horizontal channel transistors to achieve high integration, then integration density is improved, but manufacturing complexity and power consumption increase
Solution Approach 1:
The memory device is segmented into distinct functional layers: a semiconductor substrate containing source/drain regions, an insulating layer, and a variable resistance element. This segmentation simplifies the fabrication process by using standard planar semiconductor manufacturing techniques rather than complex 3D structures, while still achieving high integration density through efficient use of the planar layout.
Solution Approach 2:
The invention uses a simplified planar copy of the memory cell structure that replicates the essential functionality of more complex 3D designs. By copying the core memory function into a two-dimensional layout with separated word lines, the device achieves comparable integration density without requiring complex fabrication processes.
2Quantity of substance
If conventional resistance memory devices use complex access device structures to improve integration, then integration density is improved, but power consumption increases
Solution Approach 1:
The access path is segmented into two separate word lines (first and second word lines) that independently control the access devices. This segmentation allows for more precise voltage control and reduces unnecessary power consumption by enabling selective activation of only the required access paths, while maintaining high integration density through efficient spatial arrangement.
Solution Approach 2:
The invention changes the voltage parameters applied to different word lines to optimize power consumption. By applying different voltage levels to the first and second word lines during read and write operations, the device achieves precise control over access device activation, reducing overall power consumption while maintaining high integration density.
3Measurement precision
If conventional resistance memory devices use complex interconnection structures to access memory cells, then access precision is improved, but device complexity increases
Solution Approach 1:
The interconnection structure is segmented into separate first and second word lines that independently control different access devices. This segmentation enables precise selection of specific memory cells by activating only the required word lines, achieving high access precision while maintaining relatively simple interconnection topology compared to complex 3D routing structures.
Solution Approach 2:
The insulating layer acts as an intermediary between the semiconductor substrate and the variable resistance element, enabling clean electrical isolation and simple planar interconnections. This intermediary structure facilitates precise memory cell access through straightforward word line routing without requiring complex three-dimensional interconnection schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient fabrication and operation of resistance memory devices with improved integration and reduced power consumption, facilitating the use of resistance memory devices as next-generation memory solutions.
Implementation Method 1
the resistance memory devices use a resistance variable material of which a resistance is sharply changed according to an applied voltage to switch at least two different resistance states
Data Source
AI summary
Resistance memory device and apparatus, a fabrication method thereof, an operation method thereof, and a system including the same are provided. The resistance memory device may include a data storage unit and a first interconnection connected to the data storage unit. A first access device may be connected in series with the data storage unit and a second access device may be connected in series with the first access device. A second interconnection may be connected to the second access device. A third interconnection may be connected to the first access device to drive the first access device and a fourth interconnection connected to the second access device to drive the second access device.