Resistance-Region Diode Structure for Better Rectification
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Solution Overview
Problem
Current semiconductor devices, such as transistors and diodes, have complex manufacturing processes and structures, which hinder the development of simple and efficient diodes and transistors for use in display devices and other applications.
Innovation Solution
A diode and transistor design featuring a semiconductor layer with distinct resistance regions, where a first region has higher resistance and a second region with lower resistance, utilizing insulating and conductive layers to simplify the structure and manufacturing process, allowing for a diode-connected transistor configuration with improved rectification action and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a diode-connected transistor is used to manufacture diodes, then the number of manufacturing steps is reduced to be the same as transistor manufacturing, but the rectification action is insufficient and leakage current is high
Solution Approach 1:
The patent applies local quality by creating distinct resistance regions within the semiconductor layer. Specifically, a first region with higher resistance and a second region with lower resistance are formed in different areas of the semiconductor layer. This local differentiation of electrical properties enables the device to achieve both ease of manufacture (using standard transistor processes) and improved rectification action (through the resistance contrast between regions), resolving the technical contradiction.
2Device complexity
If a diode-connected transistor is used, then manufacturing complexity is reduced, but leakage current increases
Solution Approach 1:
The patent reduces device complexity by using a standard transistor structure manufactured through conventional processes, while simultaneously reducing leakage current through the creation of a first region with higher resistance. This high-resistance region acts as a barrier to leakage current paths, allowing the device to maintain simplicity in manufacturing while eliminating the harmful leakage effect.
3Ease of manufacture
If a simple diode structure is used, then manufacturing is simplified, but rectification performance deteriorates
Solution Approach 1:
The patent maintains manufacturing simplicity by using a conventional transistor structure that can be produced with standard fabrication processes. At the same time, rectification performance is enhanced by introducing local quality variations through the formation of a first region with higher resistance and a second region with lower resistance within the semiconductor layer. The resistance contrast between these locally differentiated regions improves rectification without complicating the overall manufacturing process.
4Ease of manufacture
If uniform resistance is used throughout the semiconductor layer, then manufacturing is easier, but rectification action is insufficient
Solution Approach 1:
The patent creates local quality variations within the semiconductor layer by forming a first region with higher resistance and a second region with lower resistance. This can be achieved through selective doping, selective oxidation, or other localized processing techniques that are compatible with standard manufacturing. The local differentiation of resistance properties enables effective rectification action while maintaining overall manufacturing feasibility through established fabrication methods.
Data Source
AI summary
A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.