Resistance Variable Memory Word Line Voltage Control

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Solution Overview

Problem

In resistance variable memory devices, the increase in word line voltage due to parasitic resistance and capacitance affects the program and read characteristics, leading to decreased performance.

Innovation Solution

The memory cell array is divided into block units, with word line drivers located between these units, and a column selection circuit is used to manage program and read currents, minimizing voltage increases through multiprogramming methods that reduce the number of memory cells connected to each word line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory cell array is configured with word lines connected to multiple memory cells, then the device can store and access data, but the word line voltage increases due to parasitic resistance and capacitance, degrading program and read characteristics

Engineering Contradiction:
Improveprogram and read characteristicsVSAvoidword line voltage increase
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The memory cell array is divided into multiple blocks, with each block containing a subset of memory cells. Word line drivers are positioned between blocks to control word lines locally. This segmentation reduces the number of memory cells connected to each word line segment, thereby reducing parasitic resistance and capacitance effects, and preventing excessive voltage increases during program and read operations.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If more memory cells are connected to each word line to increase storage capacity, then the memory density improves, but the parasitic resistance and capacitance increase, causing voltage drops that affect performance

Engineering Contradiction:
Improvememory cell densityVSAvoidparasitic resistance and capacitance
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The memory cell array is divided into multiple blocks, with each block containing a subset of memory cells. Word line drivers are positioned between blocks to control word lines locally. This segmentation reduces the number of memory cells connected to each word line segment, thereby reducing parasitic resistance and capacitance effects, and preventing excessive voltage increases during program and read operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Word line drivers are introduced as intermediary components between the main word line and the memory cell blocks. These drivers act as buffer stages that can source or sink current to compensate for voltage drops caused by parasitic resistance, thereby maintaining proper word line voltage levels even when multiple memory cells are connected.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration prevents voltage increases during program and read operations, enhancing the program and read characteristics of the resistance variable memory device by reducing the impact of parasitic resistance and capacitance.

Implementation Method 1

The resistance variable material GST can be programmed into any one of two stabilized states, that is, a crystal state and an amorphous state according to a temperature.

Methodology Applied
Scientific EffectPhase transition: Phase Change

Implementation Method 2

The resistance variable material GST is heated at a temperature higher than a melting temperature Tm by supplying a current for T1

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS7974118B2Resistance variable memory device reducing word line voltage
Publication Date: 2011.07.05 SAMSUNG ELECTRONICS CO LTD
  • US7974118B2 patent drawing
  • US7974118B2 patent drawing
  • US7974118B2 patent drawing

AI summary

A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.