Resistive Change Element Array Error Correction with Flag Bits

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Solution Overview

Problem

Resistive change element arrays face challenges in reducing parity overhead and latency while maintaining a required correctable bit error rate (BER), particularly due to high error rates and inefficient error correction methods in existing technologies.

Innovation Solution

The method involves dividing the array into subsections with distributed flag cells, using a two-step programming process to initialize and correct errors, and combining this with conventional error correction algorithms like BCH to reduce parity overhead and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error correction methods are used in resistive change element arrays, then the required correctable bit error rate is maintained, but parity overhead and latency increase

Engineering Contradiction:
Improvecorrectable bit error rateVSAvoidparity overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The array is divided into multiple subsections, each with its own flag cell. This segmentation allows error correction to be performed locally within each subsection rather than requiring global parity bits across the entire array, thereby reducing overall parity overhead while maintaining the correctable bit error rate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Flag cells are used to pre-indicate the presence and location of errors before full error correction processing. This preliminary action allows the system to quickly identify and handle erroneous cells, reducing the computational latency required for complete error correction while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If conventional error correction methods are used in resistive change element arrays, then the required correctable bit error rate is maintained, but decoding latency increases

Engineering Contradiction:
Improvecorrectable bit error rateVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Dividing the array into subsections with distributed flag cells enables parallel error detection and correction processing across multiple independent sections. This segmentation reduces the time required for complete error correction by allowing simultaneous processing rather than sequential operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The flag cells perform preliminary error indication, allowing the system to quickly identify erroneous cells before initiating full correction protocols. This preliminary detection step reduces the overall decoding latency by avoiding unnecessary processing of error-free cells.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If error correction is implemented in resistive change element arrays, then bit error rate is improved, but device complexity and overhead increase

Engineering Contradiction:
Improvebit error rateVSAvoiderror correction overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Error correction functionality is extracted into separate flag cells that are distributed throughout the array rather than using traditional parity bit structures. This extraction allows error correction to be implemented with minimal overhead by using dedicated flag cells only where errors occur, rather than adding global redundancy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The flag cells serve multiple functions: they indicate errors, provide location information for erroneous cells, and enable both detection and correction operations. This multi-functionality reduces the need for separate dedicated components for each error correction task, thereby reducing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10387244B2Methods for error correction with resistive change element arrays
Publication Date: 2019.08.20 NANTERO INC
  • US10387244B2 patent drawing
  • US10387244B2 patent drawing
  • US10387244B2 patent drawing

AI summary

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.