Resistive Memory Cache Split Write Operation
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Solution Overview
Problem
Conventional resistive memory devices, such as MRAM, face slower performance due to long write pulses that prevent read operations during write latency, leading to increased system latency and reduced memory speed.
Innovation Solution
Implementing multiple short write pulses instead of a single long write pulse allows for simultaneous read operations during write operations, utilizing a write buffer to manage and execute these pulses efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single long write pulse is used to write data in resistive memory, then the write operation is reliable, but the write latency increases and read operations cannot proceed concurrently
Solution Approach 1:
The write pulse is divided into multiple shorter sub-pulses instead of using a single long pulse. The write buffer stores data and generates multiple write sub-pulses sequentially, allowing the total write time to be distributed across multiple intervals. This segmentation enables read operations to occur during the intervals between sub-pulses, reducing the effective write latency while maintaining reliable data writing through the cumulative effect of multiple pulses.
2Reliability
If a single long write pulse is used, then data is written reliably, but system speed and efficiency are reduced
Solution Approach 1:
The write buffer enables continuous operation by overlapping write and read operations. While multiple write sub-pulses are being generated and applied to the resistive memory, the system can simultaneously accept new write commands and execute read operations. This continuous utilization of the memory system improves overall productivity and memory performance without sacrificing write reliability.
3Reliability
If read operations are blocked during write latency, then write reliability is maintained, but system efficiency decreases
Solution Approach 1:
The write buffer performs preliminary actions by storing incoming write data and managing the generation of write sub-pulses in advance. This preliminary buffering allows the system to prepare write operations without blocking read operations, as the buffer intermediates between the write command interface and the actual memory write execution. Read operations can proceed concurrently while the buffer manages write sub-pulse generation, maintaining both reliability and efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces write latency, enhances memory performance by allowing read operations to proceed concurrently with write operations, thereby improving overall system speed and efficiency.
Implementation Method 1
a write current, which exceeds a critical switching current, is applied through an MTJ. The write current exceeding the critical switching current is sufficient to change the magnetization direction of the free layer
Implementation Method 2
The electrical resistance of an MTJ depends on whether the free layer magnetization and fixed layer magnetization are parallel or anti-parallel with each other
Data Source
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AI summary
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.