Resistive Capacitance Determination for Multiple-Patterning IC Layouts
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Solution Overview
Problem
The optical proximity effect in lithography processes for integrated circuits causes features to short each other due to increasing down-scaling, leading to variations in pattern width and overlay misalignment, which results in parasitic resistive capacitance and performance variations in integrated circuits.
Innovation Solution
A method using electronic design automation (EDA) tools to simulate and model the effects of mask shifting and overlay misalignment, generating techfiles with dielectric constant values to account for varying spacings and widths, allowing for the simulation of parasitic resistive capacitance and performance variations, and selecting the best decomposition scheme to minimize performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple patterning is used to increase feature density, then feature density is improved, but optical proximity effect causes features to short each other
Solution Approach 1:
The patent divides the patterning process into multiple separate lithography steps (first lithography step, second lithography step) with separate masks. This segmentation allows each step to define patterns with adequate spacing, avoiding the optical proximity effects that would occur in a single-step process while achieving high overall feature density through the combined results of multiple steps.
2Ease of manufacture
If mask shifting occurs during lithography process, then manufacturing complexity is reduced, but overlay misalignment causes performance variations
Solution Approach 1:
The patent performs preliminary actions by defining design rules and performing simulations before actual manufacturing. The methodology includes pre-calculating expected variations, determining worst-case scenarios, and establishing design margins in advance. This allows the system to anticipate and compensate for potential mask shifting and overlay misalignment issues before they occur during production.
Solution Approach 2:
The patent changes parameters by systematically varying key variables such as mask shift amounts, overlay misalignment values, and spacing dimensions to determine worst-case performance scenarios. By analyzing performance across a range of parameter values rather than assuming ideal conditions, the methodology identifies robust design solutions that maintain performance even under adverse manufacturing conditions.
3Productivity
If down-scaling of integrated circuits is continued, then device performance is improved, but optical proximity effect increases
Solution Approach 1:
The patent applies segmentation by using multiple separate lithography steps with different masks. Each step can be optimized for specific spacing requirements, allowing the system to achieve the high feature densities needed for down-scaled devices while maintaining adequate spacing between critical features to minimize optical proximity effects.
Solution Approach 2:
The patent applies local quality by differentiating the spacing requirements for different feature types and locations within the integrated circuit. The methodology analyzes and addresses optical proximity effects locally in specific critical regions rather than applying uniform solutions across the entire device, allowing optimized spacing in areas prone to proximity effects while maintaining higher density elsewhere.
Data Source
AI summary
A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.