Resistive Multi-Phase Clock Generator for Fine Phase Control

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Solution Overview

Problem

Existing clock generators struggle to produce clock signals with fine phase steps for accurate timing control in electronic systems, and they often face frequency offset issues during clock signal distribution.

Innovation Solution

A clock generator using a multi-phase controllable oscillator with resistive components and a frequency-locked loop circuit to generate clock signals with various phases and reduce frequency offsets, incorporating a clock injection circuit and injection-locked phase rotator design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional clock generators are used, then clock signal distribution is simple, but phase control precision is insufficient

Engineering Contradiction:
Improvephase control precisionVSAvoidclock generator structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The clock generator is divided into multiple oscillator core circuits, each responsible for generating clock signals with specific phase relationships. Each core circuit includes separate resistive components and inverters that can be independently configured to achieve fine phase control steps without requiring complete redesign of the entire clock generation system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic phase control by using controllable resistive components whose resistance values can be adjusted to change the time constants of the RC circuits. This allows the phase difference between adjacent clock signals to be dynamically tuned, providing fine phase control capability while maintaining a relatively simple overall structure.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If clock signals are distributed over long distances, then system coverage is improved, but frequency offset increases

Engineering Contradiction:
Improvesystem coverageVSAvoidfrequency accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent incorporates a frequency-locked loop (FLL) circuit that continuously monitors the frequency of distributed clock signals and provides feedback control. The FLL compares the actual frequency with the reference frequency and adjusts the oscillator core circuits to minimize frequency offset, ensuring frequency accuracy is maintained even when clock signals are distributed over long distances to expand system coverage.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If resistive components are used for phase control, then phase resolution is improved, but circuit complexity increases

Engineering Contradiction:
Improvephase resolutionVSAvoidoscillator core circuit
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the phase control function into the oscillator core circuit itself by integrating resistive components directly with the inverter stages. This combination eliminates the need for separate phase control circuits, as the RC time constants formed by the resistive components and inherent capacitances directly determine the phase relationships. This approach achieves fine phase resolution while keeping the overall circuit structure compact and manageable.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9654116B1Clock generator using resistive components to generate sub-gate delays and/or using common-mode voltage based frequency-locked loop circuit for frequency offset reduction
Publication Date: 2017.05.16 MEDIATEK INC
  • US9654116B1 patent drawing
  • US9654116B1 patent drawing
  • US9654116B1 patent drawing

AI summary

A clock generator has a multi-phase controllable oscillator. The multi-phase controllable oscillator includes oscillator core circuits, and has phase nodes at which clock signals with different phases are generated, respectively. Each oscillator core circuit includes a resistive component and an inverter. The resistive component is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator, wherein clock signals generated at the first phase node and the second phase node have adjacent phases. The resistive components of the oscillator core circuits are cascaded in a ring configuration. The inverter receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator, and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.