Programmable Resistive Delay Circuit Without Bandwidth Loss
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Solution Overview
Problem
Variable delay circuits face challenges in maintaining optimal performance characteristics such as maximum data rate, noise susceptibility, resolution, and maximum operable frequency, which vary with selected delay settings, particularly in R-C responsive circuits where noise susceptibility increases at higher delays.
Innovation Solution
A programmable delay circuit design featuring two paths - a low-delay path with fewer buffers and a high-delay path with more buffers, utilizing resistive switches to achieve delay variation through resistance ratios, allowing for flexible delay settings without bandwidth reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If R-C responsive circuits are used to achieve variable delay, then delay adjustment is possible, but noise susceptibility increases as delay increases
Solution Approach 1:
The delay circuit is segmented into multiple parallel paths (first path with first delay, second path with second delay) instead of using a single R-C responsive circuit. Each path has its own delay elements, allowing the signal to be divided and recombined to achieve variable delay while maintaining signal integrity and reducing noise susceptibility through the distributed architecture.
Solution Approach 2:
Switching elements (such as MOSFETs or analog switches) are introduced as intermediaries to control the signal flow between different delay paths. These switching elements allow selective connection of different delay paths based on control signals, enabling delay adjustment without requiring the signal to pass through high-impedance R-C networks that are susceptible to noise.
2Duration of action of moving object
If delay range is increased in R-C circuits, then maximum delay is improved, but maximum data rate decreases
Solution Approach 1:
The circuit dynamically switches between different delay paths based on the desired delay setting. Instead of using a single static R-C network with fixed time constants, the system employs multiple parallel paths with different delay characteristics and uses switching elements to dynamically select or combine these paths, allowing the delay to be adjusted while maintaining optimal bandwidth for each configuration.
Solution Approach 2:
The delay characteristics are changed by altering which parallel paths are active rather than changing the parameters of a single R-C circuit. Each parallel path has predetermined delay values achieved through appropriate selection of delay elements (such as transmission line lengths or buffer stages), and the system changes the effective delay by switching between these discrete parameter sets rather than continuously adjusting R-C time constants.
3Measurement precision
If resolution is increased in variable delay circuits, then delay precision is improved, but device complexity increases
Solution Approach 1:
The delay adjustment is segmented into discrete steps by providing multiple parallel paths with progressively different delay values. Instead of using a complex continuous adjustment mechanism, the system divides the delay range into discrete intervals, with each parallel path representing a specific delay step. This segmentation achieves resolution through the number of discrete paths rather than through complex continuous control mechanisms.
Solution Approach 2:
The system provides more delay paths than the minimum required for the desired resolution, allowing for finer granularity in delay adjustment. By having additional parallel paths with intermediate delay values, the system achieves higher precision than would be required by a minimal design, while the complexity is managed through the regular, repetitive structure of the parallel paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design maintains high resolution and minimizes noise susceptibility across the delay range, enabling efficient signal delay without inverse bandwidth reduction, thus enhancing the circuit's applicability in various applications.
Implementation Method 1
The array of resistive switches of the first circuit path may be programmed to obtain a first effective resistance of the array of resistive switches of the first circuit path. The array of resistive switches of the second circuit path may be programmed to obtain a second effective resistance of the array of resistive switches of the second circuit path.
Data Source
AI summary
An example delay circuit is described that includes an input node to receive a first signal, a first circuit path, a second circuit path, an output buffer, and an output node. The first circuit path includes at least one first buffer and a first array of switches. The second circuit path includes at least one second buffer and a second array of switches. The output buffer receives a mixed output of the first circuit path and the second circuit path. The output node transmits a second signal equivalent to the first signal with a programmed delay.