Resistive Memory Device Amorphous Silicon Switching Layer
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Solution Overview
Problem
As semiconductor devices shrink, they face issues such as short channel effects, high programming voltage leading to dielectric breakdown, and compatibility problems with CMOS manufacturing for non-volatile memory devices like Flash memories, ferroelectric RAM, magneto-resistive RAM, and organic RAM, which hinder scaling and performance.
Innovation Solution
The development of resistive memory devices with a conductive silicon layer subjected to plasma etching or ion implantation to create an amorphous switching layer, combined with an active metal layer, allowing for improved data retention and reduced power consumption, enabling non-volatile memory operation without the need for refreshing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to scale memory devices, then memory density is improved, but short channel effects and dielectric breakdown occur
Solution Approach 1:
The patent changes the material parameter from conventional transistor channel materials to a resistive switching layer made of amorphous silicon oxide or silicon nitride. This material parameter change enables resistive switching behavior that is insensitive to short channel effects, allowing continued scaling to higher memory densities while maintaining reliability.
Solution Approach 2:
The patent replaces the charge-based switching mechanism of traditional FETs with a resistive switching mechanism in the memory element. This substitution eliminates the short channel effect problems that plague scaled transistors, as the resistive switching is governed by material properties rather than channel geometry.
2Ease of operation
If high voltage is applied for programming Flash memories, then programming capability is achieved, but dielectric breakdown occurs
Solution Approach 1:
The patent changes the voltage parameter from high voltage (typically 10V or more for Flash) to low voltage operation (below 5V) by utilizing the inherent resistive switching characteristics of the amorphous silicon oxide or silicon nitride layer. The resistive transition occurs at low voltages, eliminating dielectric breakdown while maintaining programming capability.
3Reliability
If new materials are used for non-volatile memory devices, then non-volatile storage capability is achieved, but compatibility with CMOS manufacturing is lost
Solution Approach 1:
The patent uses amorphous silicon oxide or silicon nitride as the resistive switching layer, which are materials already widely used in standard CMOS manufacturing for gate dielectrics and insulating layers. This material homogeneity with existing CMOS processes enables seamless integration without requiring new fabrication equipment or processes.
Solution Approach 2:
The patent employs standard CMOS-compatible deposition and annealing parameters to form the amorphous silicon oxide or silicon nitride switching layer. By using parameter ranges already established in CMOS manufacturing (deposition temperatures, annealing temperatures up to 400-450°C), the process maintains full compatibility with existing fabrication lines.
4Productivity
If device size is reduced, then memory density is improved, but programming voltage requirements cause dielectric breakdown
Solution Approach 1:
The patent changes the voltage parameter from high to low by exploiting the resistive switching mechanism in amorphous silicon oxide or silicon nitride. This material-based voltage reduction decouples memory density improvement from dielectric breakdown risk, as the low-voltage resistive switching is inherently immune to the scaling-induced breakdown problems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the power-on power-off performance and reduces power consumption in devices by maintaining resistive states without continuous power supply, while being compatible with existing CMOS manufacturing techniques, thus addressing scaling and compatibility issues.
Implementation Method 1
The conductive silicon layer is then subject to a plasma etch or ion implantation step (e.g. Argon, Oxygen, Silicon), that changes an upper region of the conductive silicon layer into an amorphous layer.
Implementation Method 2
The conductive silicon layer is then subject to a plasma etch or ion implantation step (e.g. Argon, Oxygen, Silicon), that changes an upper region of the conductive silicon layer into an amorphous layer.
Implementation Method 3
allowing for improved data retention and reduced power consumption, enabling non-volatile memory operation without the need for refreshing
Data Source
AI summary
A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.