Resistive Memory Array Resetting via Adaptive Technique Selection
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Solution Overview
Problem
Arrays of Resistive Memory (RM) cells face challenges in achieving reliable and efficient resetting due to variability in the high resistance state (HRS), leading to difficulties in distinguishing between HRS and low resistance state (LRS) states, which can result in errors and unreliable memory arrays.
Innovation Solution
A method is introduced that dynamically adjusts the reset technique for each reset operation in an array of RM cells based on the relative correction yield of available techniques, ensuring the highest efficiency and reliability by selecting the best technique for each correction step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full reprogramming is applied to reduce HRS variability, then the reliability of state distinction is improved, but the time and energy consumption increase
Solution Approach 1:
The patent applies dynamics by making the reset technique selection adaptive rather than static. The system dynamically chooses among multiple reset techniques (reprogramming, increased voltage, increased time, repeated pulse) based on real-time evaluation of relative correction yield, allowing the reset process to adapt to the actual state of each memory cell and achieve optimal performance
Solution Approach 2:
The patent changes parameters by varying voltage amplitude, pulse width, and reset technique selection based on measured relative correction yield. The system adjusts voltage pulses from nominal to increased levels, modifies pulse widths, and switches between different reset techniques to optimize both reliability and speed of resetting operations
2Reliability
If multiple reset techniques are evaluated and selected based on relative correction yield, then the efficiency and reliability of resetting is improved, but the complexity of the reset process increases
Solution Approach 1:
The patent implements feedback by measuring the relative correction yield for each reset technique and using this information to select the optimal technique for the next reset operation. The system continuously monitors the effectiveness of each technique and adjusts its selection based on this feedback, creating a closed-loop control system that improves reliability
Solution Approach 2:
The patent segments the reset process into distinct techniques (reprogramming, increased voltage, increased time, repeated pulse) that can be independently evaluated and selected. Each technique is treated as a separate option with its own characteristics, allowing the system to choose the most appropriate segment for each specific reset operation based on measured performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables fast and reliable resetting of RM cell arrays by optimizing the sequence of reset techniques, reducing bit-to-bit variability, and improving the overall reliability and efficiency of the memory array.
Implementation Method 1
the two electrodes are separated by a programmable region comprising a material able to change from crystalline to amorphous phase upon heating. In this case, the OFF state corresponds to the amorphous state of the programmable region, while the ON state corresponds to the crystalline state.
Implementation Method 2
PCRAM cells may also comprise a heater element inserted between the two electrodes and able to transform the applied voltage pulse in the heat necessary to modify the crystalline state of the programmable region.
Data Source
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AI summary
Method for resetting an array of Resistive Memory (RM) cells by applying a sequence of N reset operations, each reset operation comprising the application of a reset technique, said method comprising the following steps: - at the first reset operation (O1), performing the first reset operation (RF) by applying the reset technique having the highest relative correction yield; - at the j-th reset operation (Oj) of the N-1 subsequent reset operations, j being an integer number comprised between 2 and N, defining (Dj) a reset technique to be used at the j-th reset operation and performing the j-th reset operation (Rj).