Resistive Memory Device with Conductive Barrier Layers
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Solution Overview
Problem
Current memory technologies, such as DRAM and NAND Flash, have limitations in speed, endurance, and cost, with no universal memory combining the best attributes of both effectively, leading to a gap in the market for a non-volatile memory with DRAM-like speed and NAND Flash-like cost and endurance.
Innovation Solution
A nonvolatile memory device with a heterojunction structure using a memory layer with variable resistance, topped with a barrier layer to prevent ion conduction, and a retention layer to enhance data retention, allowing for efficient programming and reading without the need for speed-crippling error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for high-speed memory, then speed and endurance are improved, but volatility and cost increase
Solution Approach 1:
The memory device is segmented into distinct functional layers: a memory layer for data storage, barrier layers for ion confinement, and electrode layers for control. This segmentation allows each layer to be optimized independently - the memory layer for fast switching and the barrier layers for non-volatile retention, resolving the contradiction between speed and reliability
Solution Approach 2:
The invention uses composite heterostructures combining different oxide materials (e.g., HfO2 memory layer with TiO2 barrier layers) to achieve properties that single materials cannot provide. The composite structure enables both fast switching characteristics from the memory layer and non-volatile retention from the barrier layers, simultaneously achieving DRAM-like speed and Flash-like retention
2Reliability
If NAND Flash is used for non-volatile storage, then retention and cost are improved, but speed and endurance deteriorate
Solution Approach 1:
The invention changes the operational parameters of the memory layer by controlling oxygen vacancy concentration and ionic conductivity through the barrier layers. This allows the memory to achieve fast switching speeds comparable to DRAM while maintaining non-volatile retention, effectively changing the speed parameter without sacrificing retention
3Reliability
If error correction codes are added to compensate for retention issues, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The invention converts the potential harm of ion migration (which causes retention issues in conventional memories) into a beneficial mechanism for non-volatile storage. By using barrier layers to control and contain ionic movement, the memory achieves intrinsic non-volatility without requiring external error correction systems, reducing complexity while improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a cost-effective memory solution with improved speed and endurance, reducing manufacturing costs and eliminating the need for error correction codes in large storage systems, while maintaining reliable data retention.
Implementation Method 1
a first barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough
Implementation Method 2
a memory layer connected to the bottom contact, where the memory layer has a variable resistance
Data Source
AI summary
A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.