Resistive Memory Device Bit Line Activation Sequence
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Solution Overview
Problem
The existing semiconductor memory devices using resistive memory elements, such as MRAM, face limitations in achieving high-speed write operations due to the RC time constant of interconnect lines, which increases chip size and manufacturing costs when trying to reduce interconnect length for faster write times.
Innovation Solution
The semiconductor memory device includes a pair of bit lines and a word line, where the bit lines are activated first, and then the word line, allowing the node to be charged before injecting the write current, thereby reducing the influence of the RC time constant and enabling faster write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the interconnect length is reduced to decrease the RC time constant and improve write speed, then the write operation speed is improved, but the chip size increases and manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by activating the bit lines before the word line during write operations. This pre-charges the bit lines and reduces the RC time constant effect during the actual write operation, enabling faster write speeds without requiring shorter interconnects, thus avoiding increased chip size
2Speed
If the interconnect length is reduced to improve write speed, then the write operation speed is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses preliminary action by pre-activating bit lines before word lines during write operations. This reduces the RC time constant effect and improves write speed without requiring physical reduction of interconnect length, thereby avoiding increased manufacturing costs associated with smaller feature sizes
3Quantity of substance
If many memory cells are connected with a pair of bit lines to increase memory capacity, then the memory capacity is improved, but the parasitic capacitance increases and write speed decreases
Solution Approach 1:
The patent applies preliminary action by activating bit lines before word lines during write operations. This pre-charges the bit lines and reduces the impact of parasitic capacitance from multiple connected memory cells, enabling faster write speeds while maintaining high memory capacity
Solution Approach 2:
The patent uses periodic action through the sequential activation pattern of bit lines followed by word lines. This periodic sequencing allows the system to manage parasitic capacitance effects by controlling when current flows through the interconnect lines, maintaining write speed despite multiple memory cells being connected
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased speeds of both write and read operations by charging the node without current flowing through the selected memory cell, stabilizing the write current and improving operation efficiency.
Implementation Method 1
a resistive memory element which has one end and the other end, the one end being connected with the first bit line
Implementation Method 2
a selective switch element which has a current path and a control terminal
Data Source
AI summary
A semiconductor memory according to an aspect of the invention including first and second bit lines, a word line, a resistive memory element which has one end and the other end, the one end being connected with the first bit line, a selective switch element which has a current path and a control terminal, one end of the current path being connected with the other end of the resistive memory element, the other end of the current path being connected with the second bit line, the control terminal being connected with the word line, a first column switch connected with the first bit line, a second column switch connected with the second bit line, wherein the first and second bit lines is activated and then the word line is activated when starting writing or reading data with respect to the resistive memory element.