Resistive Memory Bit-Line Segmentation for Capacity Scaling
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Solution Overview
Problem
As the number of word lines in magnetic random access memory (MRAM) increases, the difference in leakage current and metal loading between memory cells worsens, leading to deteriorated read and write margins, which acts as a barrier to increasing memory capacity.
Innovation Solution
A resistive memory device is designed with a data cell array divided into two parts, each connected to different bit lines, and a reference cell array sharing word lines, using a parallel connection of metal layers to reduce leakage current and metal resistance, thereby maintaining read margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to increase memory capacity, then memory capacity is improved, but the difference in leakage current and metal loading between memory cells worsens, leading to deteriorated read and write margins
Solution Approach 1:
The bit line is divided into two separate bit lines: a first bit line connected to the lower metal layer of the MTJ and a second bit line connected to the upper metal layer of the MTJ. This segmentation allows independent control and optimization of current paths, reducing leakage current differences between near and far cells while maintaining read margins even as the number of word lines increases.
2Quantity of substance
If the number of word lines is increased to increase memory capacity, then memory capacity is improved, but metal loading and leakage current differences between near and far cells increase
Solution Approach 1:
The reference cell array is introduced as an intermediary structure that shares word lines with the data cell array. Reference cells are positioned between near and far cells to compensate for metal loading differences. The reference cells have the same structure as data cells but with fixed magnetization direction, allowing them to balance the current distribution and reduce leakage current differences across the array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and metal resistance, allowing for increased memory capacity without compromising read margin, even with an increased number of word lines.
Implementation Method 1
The write operation of MRAM is performed by activating an access transistor through the word line and applying a large current so that the data of the MTJ element can change. The value of data recorded in the MTJ element varies depending on the direction of the current.
Implementation Method 2
the second bit line comprises the first metal layer and a second metal layer
Data Source
AI summary
A resistive memory device that comprises a data cell array including a plurality of memory cells, each column of the plurality of memory cells having an electrically separated first bit line and a second bit line; a row decoder configured to decode a row address and select one or more word lines of the plurality of memory cells in response to the row address; and a column decoder configured to decode a column address and select one of the first bit line and the second bit line in response to the row address decoded by the row decoder and the column address, wherein the first bit line comprises a first metal layer, and the second bit line comprises the first metal layer and a second metal layer.