Bi-Directional Resistive Memory Cell with Capacitor for Fast Read
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Solution Overview
Problem
Current resistive memory devices exhibit slow read and write performance and are not viable substitutes for SRAM due to their minimal cell area and reliability issues, limiting their application in high-performance systems.
Innovation Solution
The integration of bi-directional resistive elements and capacitive elements in memory cells, allowing for fast read and write operations by switching between high and low resistive states, and using a write transistor and read circuit to program and sense the resistive element, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If one transistor/one resistive element or one diode/one resistive element memory cell configuration is used, then cell area is minimized, but read and write performance becomes slow (30 nanoseconds or more per operation)
Solution Approach 1:
The memory cell is segmented into functional components: a resistive element for storage, a capacitor for maintaining state, and transistors for controlled access. This segmentation allows each component to be optimized independently, with the capacitor enabling faster read operations by pre-charging the storage node without requiring additional transistors for read access.
Solution Approach 2:
The resistive element serves multiple functions: it stores data in high/low resistance states, enables bidirectional current flow for both read and write operations, and works with the capacitor to provide both non-volatility and fast read performance. This multi-functionality resolves the contradiction by making the resistive element more than just a passive storage element.
2Area of stationary object
If conventional resistive memory devices are used, then minimal cell area is achieved, but reliability becomes difficult to produce
Solution Approach 1:
A capacitor is added to the memory cell structure to cushion and maintain the stored charge state. This capacitor ensures that the resistive element maintains its state reliably over time without continuous power, providing non-volatility while also stabilizing the read operations. The capacitor acts as a buffer that prevents spurious state changes and ensures consistent operation.
3Duration of action of stationary object
If resistive memory devices are used to replace SRAM, then non-volatility is achieved, but read/write speed is too slow for high-performance systems
Solution Approach 1:
The capacitor performs preliminary action by pre-charging the storage node during write operations or maintaining charge during idle periods. This pre-charging eliminates the need for lengthy charge-up periods during read operations, significantly reducing read latency. The capacitor is charged in advance or maintained in a ready state, allowing immediate response during read operations.
4Speed
If bi-directional resistive elements with capacitive elements are integrated, then read speeds comparable to SRAM are achieved, but device complexity increases
Solution Approach 1:
The capacitor and resistive element are merged into a single memory cell structure that shares common access transistors and bitlines with conventional SRAM cells. This merging approach allows the non-volatile memory to use the same infrastructure as volatile memory, reducing overall system complexity while achieving SRAM-like read speeds through the capacitor-assisted read mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables read speeds and space requirements comparable to conventional six-transistor SRAM, allowing for efficient and compact non-volatile memory solutions.
Implementation Method 1
A bi-directional resistive memory element can be changed between a high resistive state (HRS) and a low resistive state (LRS), and the state of the resistive element produces a robust zero or one logic state to be sensed
Implementation Method 2
a capacitive element having a first terminal coupled to the internal node and a second terminal coupled to the read wordline
Data Source
AI summary
A memory cell includes a bi-directional resistive memory element, a first transistor, and a capacitive element. The bi-directional resistive memory element has a first terminal directly connected to a first power rail and a second terminal coupled to an internal node. The first transistor has a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to one of the first power rail, a second power rail, or a read wordline. The capacitive element includes a first terminal coupled to the internal node and a second terminal coupled to the read wordline.