Resistive Memory Cell Pair Segmentation for Interference Mitigation
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Solution Overview
Problem
Conventional resistive memory apparatuses experience interference between memory cells during operations, leading to decreased performance due to shared voltage lines, which affects forming, setting, and resetting operations.
Innovation Solution
The resistive memory apparatus is designed with memory cell pairs where each cell is coupled to different bit lines and source lines, allowing for individual voltage settings during operations to mitigate interference, with bit lines configured parallel to word lines and source lines extending in a different direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory cells share common source lines and bit lines, then device complexity is reduced, but interference between memory cells occurs during operations
Solution Approach 1:
The patent divides the memory cell array into multiple independent blocks, where each block has its own dedicated source lines and bit lines. This segmentation isolates the voltage signals within each block, preventing interference from propagating to other blocks. The memory device is partitioned such that first source lines and first bit lines are confined to first blocks, while second source lines and second bit lines serve second blocks, creating electrical isolation between adjacent memory regions.
Solution Approach 2:
The patent extracts the source lines and bit lines from being shared across the entire memory array and assigns them to specific blocks. By taking out the common line structure and replacing it with block-specific lines, the interference pathway is eliminated. Each block operates with its own dedicated wiring, preventing voltage signals from one block from affecting other blocks during forming, setting, or resetting operations.
2Area of stationary object
If memory cells are arranged in a compact array, then area efficiency is improved, but voltage signal interference increases during operations
Solution Approach 1:
The memory array is segmented into multiple blocks arranged in a compact configuration, with each block containing memory cells served by dedicated source lines and bit lines. This segmentation allows high-density packing of blocks while maintaining electrical isolation between them, achieving both compact area utilization and interference prevention.
Solution Approach 2:
The patent introduces block-specific source lines and bit lines as intermediaries between the memory cells in different blocks. These dedicated lines act as mediators that confine voltage signals within their respective blocks, preventing direct interference between adjacent blocks while maintaining the compact array structure.
3Ease of manufacture
If common source lines are used for multiple memory cell pairs, then manufacturing simplicity is improved, but precise voltage control during operations becomes difficult
Solution Approach 1:
The patent segments the source line configuration into block-specific lines, where each block has its own dedicated source lines. This segmentation enables independent voltage control for each block, allowing precise voltage application during forming, setting, and resetting operations without affecting other blocks, while maintaining manufacturing simplicity through a regular repeating block structure.
Data Source
AI summary
A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.