Resistive Memory Cell Segmentation for Fast Read Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices, such as RRAM, face limitations in read speed due to high resistances leading to low sense currents, which hinder their suitability for applications requiring fast read latency and high read bandwidth.
Innovation Solution
A memory cell design comprising a first and second memory element with complementary polarities, coupled through a switching element, where the read path bypasses high impedance elements, allowing for faster read operations by utilizing a resistor divider configuration to optimize voltage and current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high resistance memory elements are used in RRAM cells, then power write operations are reduced, but read speed decreases due to low sense currents
Solution Approach 1:
The memory cell is segmented into two separate memory elements (first and second memory elements) with complementary polarities, each contributing to the read path. This segmentation allows the read operation to benefit from the combined low resistance of both elements, thereby increasing sense current and read speed while maintaining the high resistance state for power-efficient write operations.
Solution Approach 2:
The patent introduces a dual-memory-element architecture that adds a dimensional aspect to the resistance characteristic. By utilizing two memory elements in series with complementary polarities, the system achieves low resistance in the read path (when both elements are in low resistance state) while maintaining high resistance for write operations, effectively resolving the contradiction between power efficiency and read speed.
2Reliability
If high ON and OFF resistance are used in RRAM cells, then write operations are more efficient, but sense currents decrease leading to slower read operations
Solution Approach 1:
The memory cell is divided into two memory elements that both contribute to the read path. During read operations, both elements are in their low resistance state, creating a combined low resistance path that generates sufficient sense current. During write operations, the complementary polarity ensures that at least one element remains in high resistance state, maintaining write efficiency and reliability.
Solution Approach 2:
The patent utilizes parameter changes in the resistance state of memory elements based on operational mode. By controlling the polarity and resistance state of each memory element independently, the system achieves low resistance (high sense current) during reads while maintaining high resistance (write efficiency) during writes, effectively resolving the contradiction between reliability and sense current quantity.
3Device complexity
If a single memory element with high resistance is used, then device complexity is reduced, but read bandwidth is limited due to low read speed
Solution Approach 1:
The memory cell is segmented into two memory elements with complementary polarities, both of which contribute to the read path. This segmentation creates a low resistance series combination during read operations, significantly increasing sense current and read speed. The increased read speed directly translates to higher read bandwidth, resolving the contradiction between device complexity and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances read speed by eliminating high impedance elements from the read path, resulting in faster read operations and improved performance for memory devices.
Implementation Method 1
Many RRAM cells have high resistances that lead to low power write or program operations at the expense of low read speed. RRAM cell 100 may have a low ON resistance (or low resistance state LRS), e.g., 1MΩ, and a high OFF resistance (or high resistance state HRS), e.g., 10MΩ.
Data Source
AI summary
A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.