Resistive Memory Cell Solid Electrolyte Segmentation
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Solution Overview
Problem
Existing resistive RAM (RRAM) technologies face challenges in achieving high storage capacity, random access, short access times, non-volatility, compatibility with CMOS logic circuits, low consumption, and efficient reading mechanisms, particularly due to low resistance ratios between conductive and non-conductive states, which lead to high leakage currents and power consumption.
Innovation Solution
A resistive memory cell structure with a solid electrolyte and metal electrodes, featuring a commutation layer and a dielectric layer, allows for a high resistance ratio between non-conductive and conductive states, enabling low reading voltages and reduced leakage currents by forming a metal-insulator-metal (MIM) structure with specific electrode materials and layer thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional resistive memory cell structure is used, then the device can be integrated with CMOS circuits, but the resistance ratio between conductive and non-conductive states is low, leading to high leakage currents and difficulty in low-voltage reading
Solution Approach 1:
The solid electrolyte layer is segmented into two distinct layers: a commutation layer for conductive filament formation and a dielectric layer for maintaining high resistance. This segmentation allows the memory cell to achieve both low resistance in the conductive state and high resistance in the non-conductive state, thereby improving the resistance ratio and reducing leakage currents.
Solution Approach 2:
The patent employs a composite structure combining a commutation layer (made of materials like GeS2, GeSe, or In2Se3) and a dielectric layer (made of materials like HfO2, SiO2, or Ta2O5). This composite material approach enables the memory cell to exhibit both conductive and insulating properties within the same solid electrolyte structure, achieving high resistance ratio while maintaining compatibility with CMOS integration.
2Loss of energy
If the resistance in the non-conductive state is increased to reduce leakage currents, then power consumption is reduced, but the reading voltage required increases, complicating low-voltage operation
Solution Approach 1:
The dielectric layer is positioned specifically between the commutation layer and the bottom electrode to provide localized high resistance where needed for reducing leakage currents, while the commutation layer maintains its conductive properties for low-voltage reading operations. This localized application of different material properties allows simultaneous achievement of low power consumption and low reading voltage.
3Reliability
If a buffer layer is added to improve thermal stability and prevent ion diffusion, then the conductive bridge reliability is enhanced, but the device complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the buffer layer functionality into the dielectric layer of the solid electrolyte structure. The dielectric layer serves both as a resistance-enhancing layer and as a barrier to prevent ion diffusion, eliminating the need for a separate buffer layer while maintaining conductive bridge stability. This merging reduces device complexity and manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the resistance ratio, allowing for accurate and energy-efficient reading of memory cells with low power consumption and reduced leakage currents, while maintaining compatibility with CMOS technology.
Implementation Method 1
the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer
Implementation Method 2
a dielectric layer... In the LRS state the memory cell is conductive for a range of voltages between 0 Volts and This range comprises the negative voltages from 0 Volts to
Data Source
AI summary
The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterized in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts andVREST2.