Resistive Memory Cells Sharing Access Device
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Solution Overview
Problem
Conventional resistive memory devices, such as phase change memory devices, require large access devices due to high current demands, resulting in a large footprint and sparse memory device population, which hinders the development of denser memory devices.
Innovation Solution
Implementing multiple memory cells per access device, with rectifying devices to prevent parallel leakage current, allowing a single access device to service multiple memory cells, thereby reducing the overall memory bit structure footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional resistive memory devices use one access device per memory cell, then each memory cell can be accessed independently, but the access device size increases due to high current demands, resulting in a large footprint
Solution Approach 1:
The patent combines multiple memory cells (specifically two memory cells per access device) to share a single access device. This merging approach reduces the total number of access devices required, thereby decreasing the overall memory bit structure footprint while maintaining independent access capability through the shared access device.
Solution Approach 2:
The access device is designed to serve multiple functions by accessing more than one memory cell. This multi-functionality allows a single access device to control multiple memory cells, reducing the density of access devices and improving the overall memory device population without sacrificing access reliability.
2Productivity
If access device size is reduced to increase memory device population density, then more memory devices can be fabricated per chip, but the access device may not support the high phase-changing currents required
Solution Approach 1:
By merging multiple memory cells under a single access device, the current handling requirement is distributed across multiple memory cells rather than concentrating the full phase-changing current through a single access device. This allows the use of smaller access devices that can still support the required current levels when shared across multiple cells.
Solution Approach 2:
The patent transitions from a one-to-one mapping (one access device per memory cell) to a many-to-one mapping (multiple memory cells per access device). This dimensional change in the access structure allows for higher population density while maintaining current support capability through the shared access device architecture.
3Area of stationary object
If multiple memory cells share a single access device, then the memory bit structure area is reduced, but parallel leakage current may occur between shared memory cells
Solution Approach 1:
The patent introduces a select device as an intermediary component between the access device and the multiple memory cells. This select device acts as a mediator that controls and isolates current flow to individual memory cells, preventing parallel leakage current from occurring between shared memory cells while allowing the access device to serve multiple cells efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of denser resistive memory devices by reducing the memory bit structure area while still supporting phase-changing currents, leading to more efficient use of space in memory arrays.
Implementation Method 1
rectifying devices to prevent parallel leakage current
Implementation Method 2
devices that store data in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied programming voltages, which in turn change cell resistance
Data Source
AI summary
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.