3D Resistive Memory Channel Structure for Lower Inter-Cell Interference
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Solution Overview
Problem
Existing resistive memory devices face challenges in reducing interference between adjacent cells and improving bias conditions for program-erase operations, particularly due to the interference caused by the channel length and RC delay issues.
Innovation Solution
The resistive memory device employs a stack structure with alternating interlayer insulating and conductive layers, featuring a channel layer with convex and concave regions, and variable resistance layers positioned only on the concave regions, which are physically spaced apart to reduce interference and improve bias conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the channel layer is formed as a continuous structure along the hole sidewall, then the structural integrity is improved, but the inter-cell interference increases due to longer channel length
Solution Approach 1:
The channel layer is segmented into multiple discrete sections along the hole sidewall, with each section corresponding to a variable resistance layer. The convex portions electrically isolate adjacent channel sections, breaking the continuous path and reducing inter-cell interference while maintaining structural integrity through the insulating material bridges.
Solution Approach 2:
Insulating material bridges are introduced as intermediary elements between adjacent variable resistance layers. These bridges form convex portions on the channel layer that electrically isolate adjacent memory cells, preventing interference while maintaining the overall structural integrity of the stacked configuration.
2Reliability
If the conductive layer thickness is increased to maintain signal strength, then the electrical conductivity is improved, but the RC delay increases due to larger capacitance
Solution Approach 1:
The patent transitions from a planar memory structure to a three-dimensional stacked configuration. Multiple memory cells are arranged vertically along the height of the hole, allowing increased signal strength through multiple conductive layers while maintaining low RC delay by keeping each individual conductive layer thin and reducing the horizontal capacitance area.
Solution Approach 2:
The conductive layers are segmented into multiple thin alternating layers rather than using fewer thick layers. This segmentation allows the structure to achieve equivalent or superior electrical conductivity through parallel conduction paths while reducing the capacitance associated with each individual conductive interface, thereby lowering RC delay.
Data Source
AI summary
A resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure through the plurality of interlayer insulating layers and the plurality of conductive layers; a plurality of insulating patterns formed on a sidewall of each of the plurality of interlayer insulating layers within the hole; a channel layer formed along a sidewall of each of the plurality of conductive layers within the hole and a sidewall of each of the plurality of the insulating patterns within the hole, the channel layer including convex regions that are adjacent to the insulating patterns and are convexly formed in relation to a central portion of the hole and including concave regions that are adjacent to the plurality of conductive layers and are concavely formed in relation to the central portion of the hole.