Resistive Memory Clamping Unit for Fast Sensing
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Solution Overview
Problem
Nonvolatile memory devices using resistive memory elements face challenges in improving read latency and precharging speed, particularly as cell density increases and miniaturization leads to increased resistive-capacitive (RC) components, which slow down sensing speed.
Innovation Solution
The implementation of a nonvolatile memory device with a clamping unit and a reference current supplying unit, along with a sense amplifier, allows for pseudo differential sensing operations by controlling clamping biases and reference currents to enhance sensing speed and reduce read latency, while also improving precharging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell density is increased and miniaturization is implemented, then storage capacity is improved, but sensing speed deteriorates due to increased resistive-capacitive (RC) components
Solution Approach 1:
The sensing operation is divided into two distinct phases: a precharge phase where the bit line is precharged to a reference voltage, and a sensing phase where the actual resistance measurement occurs. This segmentation allows the bit line to be prepared in advance, reducing the effective sensing time and compensating for the increased RC constants caused by miniaturization.
Solution Approach 2:
The bit line is precharged to a reference voltage level before the actual sensing operation begins. This preliminary action ensures that the bit line is ready for rapid sensing when the word line is activated, effectively reducing the overall read latency and maintaining high sensing speed despite increased cell density.
2Device complexity
If conventional sensing methods are used, then device simplicity is maintained, but read latency increases and sensing speed decreases
Solution Approach 1:
The bit line is precharged to a reference voltage level before the actual sensing operation begins. This preliminary action ensures that the bit line is ready for rapid sensing when the word line is activated, effectively reducing the overall read latency and maintaining high sensing speed despite increased cell density.
Solution Approach 2:
The sensing operation uses periodic clock signals to control the precharge and sensing phases. The bit line is precharged during one clock cycle and then sensed during the next, creating a rhythmic operation that optimizes timing and reduces overall read latency while maintaining simple circuit operation.
3Loss of time
If faster sensing operations are implemented, then read latency is reduced, but precharging efficiency may be compromised
Solution Approach 1:
The bit line is precharged to a reference voltage level before the actual sensing operation begins. This preliminary action ensures that the bit line is ready for rapid sensing when the word line is activated, effectively reducing the overall read latency and maintaining high sensing speed despite increased cell density.
Solution Approach 2:
The sensing amplifier compares the actual bit line voltage with the reference voltage during the sensing phase, providing feedback that enables rapid determination of the memory cell state. This feedback mechanism allows for quick sensing decisions without requiring extended precharging times, thus maintaining both fast read latency and precharging efficiency.
Data Source
AI summary
A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.