Resistive Memory Common Plate Switching Reduction
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Solution Overview
Problem
Current non-volatile memory technologies, such as flash memory, face limitations in power consumption and operation speed, while resistive switching memory technologies like ReRAM and CBRAM offer lower power and higher speeds but require efficient control methods to optimize performance.
Innovation Solution
A resistive switching memory device with reduced common plate switching, utilizing a plurality of resistive memory cells programmable between low and high resistance states, and a command detector/write controller to perform optimized write operations, allowing for reduced power consumption and write cycle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional write operations are used on resistive memory cells, then complete programming and erasing can be achieved, but power consumption increases and write cycle times lengthen due to unnecessary switching of common plates
Solution Approach 1:
The command detector identifies write commands in advance and the write controller prepares the common plate switching sequence before actual write operations begin. This preliminary detection and preparation allows the system to optimize the switching sequence, preventing unnecessary common plate transitions that would increase power consumption and extend write cycle times.
Solution Approach 2:
The write controller dynamically adjusts the switching sequence of common plates based on the specific write command detected. Instead of following a fixed switching pattern, the system adapts the common plate activation sequence to match the actual write operation requirements, reducing unnecessary switching events and optimizing both power consumption and write speed.
2Reliability
If multiple write operations are performed sequentially on resistive memory cells, then data can be programmed and erased, but the repeated switching of common plates increases power consumption
Solution Approach 1:
The command detector captures write command information in advance, allowing the write controller to pre-determine the optimal switching sequence for multiple write operations. This preliminary action enables the system to consolidate common plate switching events and eliminate redundant transitions, ensuring reliable data programming and erasing while minimizing energy loss from unnecessary switching.
Solution Approach 2:
The write controller changes the switching parameters of common plates based on the detected write commands. By adjusting which common plates are activated and when, the system optimizes the sequence to perform multiple write operations with minimal switching events, reducing energy consumption while maintaining data integrity.
3Ease of operation
If conventional write control methods are used, then all resistive memory cells can be accessed, but the switching overhead of common plates reduces write operation speed
Solution Approach 1:
The command detector and write controller work together to pre-identify write commands and prepare the optimal switching sequence before write operations commence. This preliminary preparation allows the system to execute write operations more quickly by avoiding delays from unnecessary common plate switching, while still maintaining full accessibility to all resistive memory cells through proper selection signals.
Solution Approach 2:
The write controller dynamically optimizes the common plate switching sequence based on the specific write command requirements. By adapting the switching pattern to match the actual operation needs, the system maintains ease of accessing any memory cell while significantly reducing the switching overhead that would otherwise slow down write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes power usage and write cycle times by optimizing the switching of resistive memory cells between low and high resistance states, enhancing the performance of ReRAM and CBRAM technologies.
Implementation Method 1
each of the resistive memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction
Data Source
AI summary
Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.