Resistive Memory Compensation Circuit for Leakage Current Mitigation
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Solution Overview
Problem
Current memory devices face challenges in maintaining accurate voltage application to selected memory cells due to voltage drops caused by leakage currents in non-selected memory cells, leading to deviations in voltage distribution and reduced stability of data storage.
Innovation Solution
A compensation circuit is introduced, comprising a sampling circuit that senses leakage currents and a holding circuit that compensates for voltage drops by generating a sampling value and applying it to selected bit lines, ensuring accurate voltage application and reducing deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a predetermined voltage is applied to selected bit lines connected to selected memory cells, then memory operations can be performed on selected cells, but voltage drops occur due to leakage currents flowing through non-selected memory cells causing inaccurate voltage application
Solution Approach 1:
The sampling circuit performs preliminary measurement of leakage current before the main memory operation. By sensing the leakage current that will flow through non-selected memory cells during the voltage application phase, the system can predict and compensate for the resulting voltage drop in advance, ensuring accurate voltage application to selected memory cells.
Solution Approach 2:
The holding circuit uses feedback from the sampling circuit to dynamically adjust the compensation voltage. The sampling value obtained from measuring leakage current is fed back to the holding circuit, which then applies an appropriate compensation voltage to counteract the voltage drop, maintaining stable and accurate voltage levels during memory operations.
2Manufacturing precision
If leakage current sensing and compensation is implemented, then voltage accuracy to selected memory cells is improved, but device complexity increases due to additional sampling and holding circuits
Solution Approach 1:
The sampling circuit and holding circuit are integrated into the existing memory device architecture, sharing common components such as bit lines and control logic. The sampling circuit utilizes the same bit line infrastructure already present in the memory device, and the holding circuit coordinates with existing voltage generation and control circuits, thereby reducing the addition of separate independent components and minimizing overall structural complexity.
Solution Approach 2:
The sampling circuit serves multiple functions: it senses leakage current, generates sampling values, and provides feedback information for compensation. The holding circuit also performs multiple roles by holding the sampling value, generating compensation voltage, and coordinating with the control logic circuit. This multi-functionality reduces the need for dedicated separate components for each function, thereby simplifying the overall device structure despite the added capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compensation circuit effectively applies a target voltage to selected memory cells, improving resistance distribution and stability of data storage in resistive memory devices by mitigating the impact of leakage currents from non-selected cells.
Implementation Method 1
a sampling circuit that generates a sampling value by sensing a leakage current that is applied to non-selected memory cells from among the memory cells
Implementation Method 2
a holding circuit that compensates for a voltage applied to the selected bit lines, based on the sampling value
Data Source
AI summary
A memory device includes: a memory cell array, multiple bit lines, a compensation circuit, a holding circuit, and a control logic circuit. The memory cell array includes multiple memory cells. Each of the bit lines is connected to at least one of the memory cells. Among the bit lines, a predetermined voltage is applied to selected bit lines connected to selected memory cells. The compensation circuit includes a sampling circuit that generates a sampling value by sensing a leakage current applied to non-selected memory cells from among the plurality of memory cells. The holding circuit compensates for a voltage applied to the selected bit lines, based on the sampling value. The control logic circuit outputs a sampling-enable signal that controls enabling of the sampling circuit and a holding-enable signal that controls enabling of the holding circuit.