Resistive Memory Contact Layer Planarization
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Solution Overview
Problem
Resistive nonvolatile storage devices in memory arrays experience increased variations in characteristics and failed bits at the end portions, leading to instability and reduced capacity due to surface unevenness and polishing effects during CMP processes.
Innovation Solution
A resistive nonvolatile storage device configuration with a contact layer covering the interlayer insulating layer and a contact plug, where the conductive layer is polished to maintain the contact layer's coverage, reducing surface unevenness and variations by preventing polishing of the interlayer insulating layer, and a manufacturing method involving specific electrode and resistance change layer structures to stabilize resistance changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to polish the interlayer insulating layer, then surface flatness is improved, but surface unevenness and polishing effects cause variations in characteristics and failed bits at end portions
Solution Approach 1:
A planarization layer is introduced as an intermediary between the interlayer insulating layer and the electrode. This planarization layer absorbs the surface unevenness caused by CMP polishing, providing a flat upper surface for the electrode while not affecting the underlying interlayer insulating layer. This resolves the contradiction by decoupling the surface flatness requirement from the interlayer insulating layer, eliminating the polishing-induced variations and failed bits.
2Quantity of substance
If memory array capacity is increased, then storage capacity is improved, but variations in characteristics and failed bits increase at end portions
Solution Approach 1:
The planarization layer serves as a mediator that isolates the electrode from the CMP-induced surface unevenness. This allows the memory array to be scaled up in capacity without the end portion failures that would otherwise limit array size. The planarization layer ensures uniform electrode formation across the entire array, enabling high-capacity storage while maintaining reliability.
3Device complexity
If electrode is formed directly on interlayer insulating layer, then device complexity is reduced, but surface unevenness causes variations in resistance changes
Solution Approach 1:
The planarization layer is positioned between the interlayer insulating layer and the electrode, serving as a mediator that provides a flat surface for electrode formation. This intermediate layer eliminates the direct exposure of the electrode to CMP-induced unevenness, ensuring consistent resistance changes across all memory elements while adding minimal structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces characteristic variations and failed bits in memory arrays, enhancing the stability and capacity of large-capacity resistive nonvolatile storage devices by minimizing surface unevenness and maintaining consistent resistance changes.
Implementation Method 1
surface unevenness and polishing effects during CMP processes
Implementation Method 2
selectively generating an oxidation reaction and a reduction reaction at an interface between a transition metal oxide layer having a high oxygen content and an electrode disposed in contact with the transition metal oxide layer
Implementation Method 3
selectively generating an oxidation reaction and a reduction reaction at an interface between a transition metal oxide layer having a high oxygen content and an electrode disposed in contact with the transition metal oxide layer
Data Source
AI summary
A resistive nonvolatile storage device includes a first interlayer insulating layer provided above a substrate, a contact hole penetrating through the first interlayer insulating layer, a contact layer wholly covering a bottom surface and a sidewall surface of the contact hole and extending to at least partially cover an upper surface of the first interlayer insulating layer, a contact plug filled in the contact hole, an upper surface of the contact plug being positioned below an upper surface of the contact layer, a lower electrode provided on both the contact plug and the contact layer that is provided on the part of the upper surface of the first interlayer insulating layer, and a resistance change layer provided on the lower electrode, and an upper electrode that is provided on the resistance change layer.