Resistive Memory Read/Write Control Circuit Transistor Reduction
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Solution Overview
Problem
Conventional read/write circuits for resistive type memory require multiple transistors in current paths, leading to increased parasitic capacitance, power consumption, and reduced read/write speed due to the need for larger transistors to maintain current strength.
Innovation Solution
A read/write control device with a reduced number of transistors in current paths, utilizing serially connected PMOS and NMOS transistors in logic units and transistor sets, and a guide transistor to minimize transistor count and optimize current flow, along with pre-charging or pre-discharging bit and source lines to manage voltage stress on variable resistance elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple transistors are used in current paths for read/write operations, then the circuit can provide sufficient current strength, but parasitic capacitance increases and read/write speed decreases
Solution Approach 1:
The patent extracts and eliminates unnecessary transistors from the current path. Specifically, it removes selection multiplexers during read operations, reducing the number of transistors from 4 or more to just 1 transistor per current path. This extraction of redundant components directly reduces parasitic capacitance while maintaining sufficient current strength through optimized transistor sizing.
Solution Approach 2:
The patent implements dynamic circuit configuration where the same circuit structure adapts its complexity based on operation type. During write operations, full multiplexer structures are activated for column selection. During read operations, the circuit dynamically simplifies by disabling multiplexers and using direct transistor switching. This dynamic adaptation allows the circuit to maintain current strength when needed while minimizing parasitic capacitance during read operations.
2Power
If multiple transistors are used in current paths, then current strength can be maintained, but power consumption increases
Solution Approach 1:
The patent removes redundant transistors from the current path during read operations, eliminating the selection multiplexers that would otherwise be present. This reduction from multiple transistors to a single transistor per path directly reduces the number of gate switches and associated power consumption while maintaining the necessary current strength through optimized transistor dimensions.
Solution Approach 2:
The patent discards the use of selection multiplexers during read operations, recovering power by eliminating the switching activity and parasitic charging/discharging of multiple transistor gates. The circuit recovers performance by using larger, more efficient transistors in the simplified path to maintain current strength with fewer components.
3Ease of operation
If selection multiplexers are used during read operations, then column selection can be performed, but additional multiplexers increase circuit complexity
Solution Approach 1:
The patent makes the transistor sets serve multiple functions. The same transistor sets that perform column selection during write operations are reused during read operations without requiring separate selection multiplexers. This multi-functionality eliminates the need for additional dedicated read-path multiplexers, reducing circuit complexity while maintaining full column selection capability through the word line and transistor gate control.
Solution Approach 2:
The patent merges the read and write path control mechanisms. Instead of having separate selection multiplexers for read operations and relying on write-path multiplexers for write operations, the circuit uses a unified transistor switching mechanism controlled by word lines and gate signals that serves both read and write functions. This consolidation eliminates redundant components and simplifies the overall circuit architecture.
Data Source
AI summary
A read/write control device of resistive type memory includes a first logic unit and a second logic unit. In a bit line driving circuit, the first logic unit is connected to a gate of a first transistor set for outputting a bit line signal, wherein the first transistor set includes one PMOS and one NMOS serially connected to each other. The first logic unit has a pair of input terminals respectively for receiving a column selection signal and receiving a control signal that decides if data “0” is to be written. In a source line driving circuit, the second logic unit is connected to a gate of a second transistor set for outputting a source line signal, wherein the second transistor set includes one PMOS and one NMOS serially connected to each other. The second logic unit has a pair of input terminals respectively for receiving a column selection signal and receiving a control signal that decides if data “1” is to be written.