Resistive Memory Monotonic Counter With Distributed Bit Switching
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Solution Overview
Problem
Conventional monotonic counters in non-volatile memory face limitations in longevity and security due to the reliance on binary coded decimal (BCD) algorithms, which limit the endurance life of least significant bits, making them vulnerable to hacking and compromising data integrity.
Innovation Solution
Implementing monotonic counters in non-volatile resistive switching memory using non-BCD algorithms and a combination of M adder bits, N base multiplier bits, and optional interval bits, which distribute the switching frequency across multiple bits, enhancing longevity and security by reducing the frequency of bit changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCD algorithms are used in monotonic counters, then data integrity is maintained, but the endurance life of least significant bits is limited and security is compromised
Solution Approach 1:
The counter is divided into multiple bits (adder bits and base multiplier bits) that share the switching load. Instead of one bit handling all count transitions, the switching frequency is distributed across multiple bits, reducing wear on individual bits and extending overall counter lifespan while maintaining data integrity through hardware implementation
2Ease of operation
If BCD algorithms are used in monotonic counters, then counting function is achieved, but security against hacking is compromised
Solution Approach 1:
The patent replaces software-based BCD counting algorithms with a hardware-implemented monotonic counter using resistive switching memory. This substitution eliminates software vulnerabilities and provides hardware-level security, as the counter operates at the physical hardware level rather than through software that can be compromised
Solution Approach 2:
By distributing the counting function across multiple hardware bits rather than relying on a single software algorithm, the system achieves better security. The hardware implementation with distributed bit architecture makes it more difficult to compromise compared to software-based approaches
3Device complexity
If switching frequency is concentrated in least significant bits, then counting is simplified, but longevity is reduced
Solution Approach 1:
The counting function is segmented across multiple bits with different roles: adder bits for fine-grained counting and base multiplier bits for larger increments. This segmentation distributes switching frequency across the bit array, reducing wear on any single bit while maintaining relatively simple counting logic through the hardware architecture
Solution Approach 2:
The patent changes the parameter of switching frequency distribution by using non-BCD algorithms that spread transitions across multiple bits. This parameter change transforms the counting behavior from concentrating switches in LSB to distributing them, thereby extending longevity while accepting slightly more complex bit manipulation logic
Data Source
AI summary
A monotonic counter implemented at least in part in non-volatile memory hardware is described herein. Compared with software counting algorithms, the disclosed embodiments significantly enhance security of disclosed monotonic counters. In some aspects of the disclosed embodiments, a non-binary coded decimal (BCD) counting algorithm can be utilized in whole or in part to enhance longevity of non-volatile memory cells storing monotonic counter values. Various aspects of the present specification disclose both a monotonic increase counter, and a monotonic decrease counter.