Monolithic Resistive Memory Integration for CPU Parallelism
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Solution Overview
Problem
Current integrated circuit technologies face limitations in achieving high memory parallelism and efficient data throughput due to the constraints of traditional memory architectures, particularly in scaling down feature sizes and maintaining power efficiency.
Innovation Solution
The integration of a monolithic integrated circuit with multiple independent process cores and embedded non-volatile resistive memory, where resistive memory arrays are fabricated above the substrate, enabling close proximity to logic circuits and providing access circuitry for independent operational access, thereby facilitating massive parallelism and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory architectures are used, then device complexity is manageable, but memory parallelism and data throughput are limited
Solution Approach 1:
The memory system is divided into multiple independently accessible sub-arrays, each capable of being accessed by different process cores simultaneously. This segmentation enables massive memory parallelism by allowing concurrent access to multiple memory regions, directly resolving the contradiction between limited parallelism and manageable complexity.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking, placing resistive memory arrays above the substrate in vertical layers. This dimensional change dramatically increases memory capacity and parallelism without proportionally increasing footprint complexity, enabling high-density integration with multiple process cores.
2Quantity of substance
If feature sizes are scaled down to increase density, then memory capacity improves, but power efficiency deteriorates
Solution Approach 1:
The patent replaces traditional capacitive storage mechanisms with resistive switching elements that maintain state through resistance changes rather than charge storage. This substitution eliminates continuous refresh operations required by DRAM, significantly improving power efficiency while enabling higher density through smaller feature sizes.
Solution Approach 2:
The invention utilizes variable resistance states in resistive memory cells to encode data, transitioning from voltage-based to resistance-based storage. This parameter change enables non-volatile operation with lower power consumption and allows scaling to advanced technology nodes while maintaining power efficiency.
3Productivity
If large main memory capacities are implemented, then data throughput increases, but access latency increases
Solution Approach 1:
By dividing large memory capacity into multiple smaller sub-arrays that can be accessed independently and concurrently, the system achieves high throughput without proportional latency increase. Multiple process cores can access different sub-arrays simultaneously, effectively parallelizing memory operations.
Solution Approach 2:
The patent implements cache memory hierarchies and predictive pre-fetching mechanisms that prepare data before it is needed by processing cores. This preliminary action reduces effective access latency by having data ready in advance, allowing large memory capacities to be accessed with latency comparable to smaller systems.
Data Source
AI summary
Disclosed is a monolithic integrated circuit (IC) computing device with multiple independent process cores (multicore) and embedded, non-volatile resistive memory serving as system memory. The resistive system memory is fabricated above the substrate, and logic circuits embodying the process cores are fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory, and circuitry embodying memory controllers, routing devices and other logic components is provided at least in part on the substrate. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and operable with many process cores, all on a single die. This monolithic integration provides close physical proximity between the process cores and main memory, facilitating significant memory parallelism, reduced power consumption, and eliminating off-chip main memory access requests.